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MDS213 12-Port 10/100Mbps + 1Gbps Ethernet Switch
Data Sheet Features
* * 12 10/100Mbps Autosensing, Fast Ethernet ports with Reduced MII Interface Single Gigabit Ethernet port
* Supports both GMII and integrated Physical Coding Sublayer with Ten Bit Interface (TBI) logic to interface directly with Gigabit transceivers
October 2003
Ordering Information MDS213CG 456 Pin HSBGA
0C to 70C - Protocol filtering - Local port filtering - Aging control for secure MAC addresses - Provides 256-port and ID Tagged Virtual LANs (VLANs) 802.1Q * * * ID Tagging Insertion/Extraction Supports IP Multicasting through IGMP Snooping XpressFlow Quality of Service (QoS), IEEE 802.1p, supports 4 Level transmission priorities, weighted fair queuing based packet scheduling, user mapping of priority levels and weights Full duplex Ethernet IEEE 803.2x flow control minimizes traffic congestion Supports back-pressure flow control for half duplex mode Flooding and Broadcasting control Link status and TX/RX activity through serial LED interface Up to 64K using management CPU memory
*
Two-chip solution for 24+2 configuration - 32-bit wide bi-directional pipe at 100Mhz provides 6.4Gbps pipe to connect two MDS213 chips Supports up to 6.548 Mpps system throughput using non-blocking architecture High performance Layer 2 packet forwarding and filtering at full wire speed. Very low latency through single store and forward at ingress port and cut-through switching at destination ports Port Trunking and Load Sharing for high bandwidth links between switches On-chip address lookup engine and memory for up to 2K MAC addresses Parallel Flash interface for fast self initialization Supports packet filtering and port security - System wide filtering - Static MAC destination and source address filtering - VLAN for multicast/broadcast filtering
* * *
* * * *
* * * * *
SRAM
CPU
Flash
CPU BUS
SRAM 64 bit
MDS213 XPipe 32 bit
MDS213 64 bit
SRAM
4x 4 x Fast 10/100 10/100 4 x 10/100 Ethernet 1G Fast Fast Ethernet Ethernet G Ethernet
1G G Ethernet
4 x 10/100 4x 4x FastFast 10/100 Ethernet10/100 Ethernet Fast Ethernet
24 + 2 System Configuration
Figure 1 - 24 10/100Mbps + 2Gbps Port System Configuration 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
MDS213
* * Up to 16K using external buffer memory Standard software modules available:
* Browser, GUI, and text menu * IEEE 802.1d Spanning Tree Algorithm
Data Sheet
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SNMP management Telnet for remote control console Automatic Booting via TFTP Protocols. Remote Monitoring (RMON) and storage for a management agent
* IGMP for IP multicast * GVRP, GMRP
*
Packaged in 456-Pin Ball Grid Array
Description
The Zarlink MDS213 is a 12-port 10/100Mbps + 1Gbps high-performance, non-blocking Ethernet switch with onchip address memory and address lookup engine. A single chip provides 12 - 10/100Mbps ports and 1 - 1000Mbps port. The MDS213 can be utilized in both managed and unmanaged switching applications. The 3.2 Gbps XPipe allows a high-speed connection between two MDS213 chips, providing a optimal, low-cost, workgroup switch with 24 10/100 Fast Ethernet ports and 2 Gigabit Ethernet ports. In half-duplex mode, all ports support back pressure flow control to minimize the risk of losing data for long activity bursts. In full-duplex mode, IEEE 802.3x frame based flow control is used. With full-duplex capabilities, each Fast Ethernet ports supports 200Mbps aggregate bandwidth connections, while the Gigabit Ethernet port supports 2 Gbps to desktops, servers, or other high-performance switches. The Physical Coding Sublayer is integrated onchip with Ten Bit Interface (TBI) and this Physical Coding Sublayer can be bypassed when the GMII interface is used. The MDS213 supports port trunking/load sharing on the 10/100Mbps ports. Port trunking/load sharing can be used to group ports between interlinked switches for increased system bandwidth. Ports within a trunk must reside within a single MDS213, such that trunks may not be configured across two switches. The on-chip address lookup engine supports up to 2K MAC addresses and up to 256 IEEE 802.1Q Virtual LANs (VLAN). Each port may be programmed to recognize VLANs, and will transmit frames along with their VLAN Tags, for interoperability, to systems that support VLAN Tagging. Each port independently collects statistical information using SNMP and the Remote Monitoring Management Information Base (RMON - MIB). Access to these statistical counter/registers are provided via the CPU interface. SNMP Management frames may be received and/or transmitted via the CPU interface and thus creates a complete network management solution. The MDS213 utilizes cost effective, high performance, pipelined SBRAM to achieve full wire speed on all ports simultaneously. Data is buffered into memory, using 0-128 byte bursts, from the ingress ports, and transferred to an internal transmit FIFO, before being sent from the frame memory to the egress output ports. Extremely high memory bandwidth is therefore achieved, which allows each of the ports to be active without creating a memory bottleneck. The MDS213 is fabricated with 2.5 V technology, where the inputs are 3.3V tolerant and the outputs are capable of directly interfacing to Low-Voltage TTL levels. The Zarlink MDS213 is packaged in a 456-pin Ball Grid Array.
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MDS213
32 CPU Interface Registers Switch Control Memory 2k SRAM HISCTM
Data Sheet
Search Engine 32
SBRAM Frame Engine Frame Buffer Memory 64 Frame Memory Interface GMAC
Reduced Xpipe Engine 32
3.2Gbps XPipeTM
Twelve 10/100 MACs
GMII/PCS(TBI) Interface
LED Xface
RMII
GMII or PCS
Figure 2 - System Block Diagram Note: All registers are 32-bit width. The Control Bus is 32-bits wide and the Memory Bus is 64-bits wide. The MDS212 contains 12 Fast Ethernet Ports. The LED interface has 3 output signals (1 data and 2 control). The XPipe is 32-bits wide.
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MDS213 Table of Contents
Data Sheet
1.0 Ball Signal Descriptions and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Ball Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 Ball-Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.0 The Media Access Control (MAC) and GIGABIT (GMAC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 MAC/GMAC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 The Inter-frame Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 Ethernet Frame Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 Collision Handling and Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5 Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.6 VLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7 MAC Control Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.8 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.8.1 Collision-Based Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8.2 IEEE 802.3x Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.9 Frame Bursting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.0 Frame Engine Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 Transmission scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.0 Frame Buffer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 Frame Buffer Memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 Frame Buffer memory usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.1 Memory Allocation of a Managed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.2 Frame Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.3 Transmission Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.4 Mailing List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.5 VLAN Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.6 VLAN MAC Association Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.7 Unmanaged System memory allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 The Frame Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.1 Local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Layer 2 Search Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.1 VLAN Unaware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.2 VLAN Aware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 Address and VLAN learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 Flooding and Packet Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4 Packet Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5 Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.6 IP Multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0 The High Density Instruction Set Computer (HISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 HISC architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 HISC Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3.1 Resource Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3.2 Resource Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.3 Switching Database Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.4 Send and Receive Frames for Management CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.5 Communication Between HISC and Switching Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.6 Communication Between Search Engine and HISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.7 Communication Between HISC and Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 Communication Between Management CPU and HISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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MDS213 Table of Contents
Data Sheet
7.4.1 CPU-HISC Communication Using Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4.2 Mailbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4.3 CPU-HISC MAIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4.4 HISC-CPU Mail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.0 The XPipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 XPipe Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2 XPipe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.0 Physical Layer (PHY) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1 Reduced MII (RMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 The Gigabit Media Independent Interface (GMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.1 The MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.2 MII Command and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3 The Physical Coding Sublayer with Ten Bit Interface (TBI): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.0 The Control Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 External CPU Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1.1 Power On/Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.2 CPU Bus Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.3 Address And Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.4 Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.5 Input/Output Mapped Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.6 Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 Control Bus Cycle Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.3 The CPU Interface in Unmanaged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.3.1 Arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.4 CPU Interface in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.4.1 CPU Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.0 The LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1 LED interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1.1 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1.2 Port Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1.3 LED Interface Time Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.0 Data Forwarding Protocol and Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1.1 Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1.2 Unicast Frame Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1.3 Multicast Frame Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2 Flow for Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2.1 Unicast Data Frame to Local Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2.2 Unicast Data Frame to Remote Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2.3 Multicast Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3 Flow for CPU Control Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.1 CPU Transmitting Unicast CPU Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.2 CPU Transmitting Multicast CPU Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.3 CPU Receiving Unicast Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.4 CPU Receiving Multicast frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.0 Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.2 Physical Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2.1 Setting Register For Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2.1.1 APMR- Port Mirroring Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.0 Virtual Local Area Networks (VLAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2 VLAN Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.1 Static Definitions of VLAN Membership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.2 Dynamic Learning of VLAN Membership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.3 Dynamic Learning of Remote VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.4 MDS213 Data Structures For VLAN Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.2.4.1 VLAN ID Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.2.4.2 VLAN MAC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.2.4.3 VLAN Port Mapping Table (VMAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.2.4.4 Port VLAN ID (PVID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.0 IP Multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.2 IGMP and IP Multicast Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.3 Implementation in MDS213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.3.1 MCT Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.3.1.1 MCT Structure For Unicast Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.3.2 MCT structure for IP Multicast Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.0 Quality of Service (QOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16.1 Weighted Round Robin Transmission Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16.2 Buffer Management Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1 Unicast Packet Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.2 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2.1 Select One Forwarding Port per Trunk Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2.2 Blocking Multicast Packets Back to the Source Trunk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17.3 MAC Address Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.0 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.1 Register MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.2 Register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1 Device Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1.1 GCR - Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1.2 DCR0 - Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18.2.1.3 DCR1 - Signature, Revision & ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18.2.1.4 DCR2 - Device Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18.2.1.5 DCR3 - Interfaces Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18.2.1.6 MEMP - Memory Packed Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18.2.2 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18.2.3 Buffer Memory interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.2.3.1 MWARS - Memory Write Address Register - Single Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.2.3.2 MRARS - Memory Read Address Register - Single Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.2.3.3 Address Registers For Burst Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 18.2.3.4 Memory Read/Write Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18.2.3.5 VTBP - VLAN ID Table Base Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18.2.3.6 MBCR - Multicast Buffer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.3.7 AMA - RAM Counter Block Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.3.8 Reserve Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.3.9 Reserve Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4 Frame Control Buffers Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.1 FCBSL - FCB Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.2 FCBST - FCB QUEUE - Buffer Low Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.3 BCT - (FCB) Buffer Counter Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.4.4 BCHL - Buffer Counter Hi-low Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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18.2.5 Queue Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.5.1 CINQ - CPU Input Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.5.2 COTQ - CPU Output Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18.2.6 Switching Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18.2.6.1 HPCR - HISC Processor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18.2.6.2 HMCL0 - HISC Micro-code Loading Port - Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18.2.6.3 HMCL1 - HISC Micro-code Loading Port - High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18.2.6.4 MS0R Micro Sequence 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18.2.6.5 MS0R Micro Sequence 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18.2.6.6 Flooding Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.2.6.7 MCAT - MCT Aging Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.2.6.8 Tpmxr - Trunk Port Mapping Table Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.6.9 TPMTD - Trunking Port Mapping Table Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.6.10 PTR - Pacing Time Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.6.11 MTCR - MCT Threshold & Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7 Link List Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7.1 LKS - Link List Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7.2 AMBX - Mail Box Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7.3 AFML - Free Mail Box List Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.8 Access Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.8.1 AVTC - VLAN Type Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.8.2 AXSC - Transmission Scheduling Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.8.3 ATTL - Transmission Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 18.2.9 MII Serial Management Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 18.2.9.1 AMIIC - MII Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 18.2.9.2 AMIIS - MII Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10 Flow Control Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.1 AFCRIA - Flow Control RAM Input Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.2 AFCRID0 - Flow Control RAM Input Data 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 18.2.10.3 AFCRID1 - Flow Control RAM Input Data 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 18.2.10.4 AFCR - Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 18.2.10.5 AMAR[1:0] - Multicast Address Reg. For MAC Control Frames. . . . . . . . . . . . . . . . . . . . . 89 18.2.10.6 AMCT - MAC Control Frame Type Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 18.2.10.7 ADAR [1:0] - Base MAC Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 18.2.10.8 ADAOR0 - MAC Offset Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.2.10.9 ADAOR1 - MAC Offset Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.2.10.10 ACKTM - Timer For SOF Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.10.11 AFCHT10 - Flow Control Hold Time Of 10Mbps Port . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.10.12 AFCHT 100 - Flow Control Hold Time Of 100Mbps Port . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.10.13 AFCHT1000 - Flow Control Hold Time of Giga Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 18.2.10.14 AFCOFT10 - Flow Control Off Time of 10Mbps PROT . . . . . . . . . . . . . . . . . . . . . . . . . . 92 18.2.10.15 AFCOFT100 - Flow Control Off Time of 100Mbps PORT . . . . . . . . . . . . . . . . . . . . . . . . 92 18.2.10.16 AFCOFT1000 - Flow Control Off Time of Giga Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11 Access Control Function Group 2 (Chip Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.1 APMR- PORT MIRRORING REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.2 PFR - Protocol Filtering Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.3 THKM [0:7] - Trunking Forwarding Port Mask 0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 18.2.11.4 IPMCAS - IP Multicast MAC Address Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18.2.11.5 IPMCMSK- IP Multicast MAC Address Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 18.2.11.6 CFCBHDL - FCB Handle Register For CPU Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 18.2.11.7 CPU Access Internal RAMs (Tables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 18.2.11.8 CPUIRCMD - CPU Internal RAM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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MDS213 Table of Contents
Data Sheet
18.2.11.9 CPUIRDAT - CPU INTERNAL RAM DATA REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . 98 18.2.11.10 CPUIRRDY - Internal Ram Read Ready For CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18.2.11.11 LEDR- LED Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18.2.12 Ethernet MAC Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18.2.12.1 ECR0 - ECR0 - MAC Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.2.12.2 ECR1 - MAC Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.2.12.3 ECR2 - MAC Port Interrupt Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.2.12.4 ECR3 - MAC Port Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 18.2.12.5 ECR4 - Port Status Counter Wrapped Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 18.2.12.6 PVID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 19.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 19.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 19.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 20.0 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 20.1 XPIPE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 20.2 CPU BUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 20.3 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Zarlink Semiconductor Inc.
MDS213 List of Figures
Data Sheet
Figure 1 - 24 10/100Mbps + 2Gbps Port System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3 - Frame with Carrier Extension and Frame Bursting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 4 - Frame Buffer Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 5 - Memory Map of Managed System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 6 - Memory Map of an Unmanaged System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 7 - Typical Packet Header Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 8 - XPipe System Block Diagram for the MDS213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 9 - XPipe Message Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 10 - Basic Timing Diagram of XPipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 11 - CPU Interface Configuration in Managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 12 - Control Bus Configuration in Unmanaged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 13 - Control Bus I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 14 - Block Diagram of the Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 15 - Little and Big Endian Byte Swapping Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 16 - An example of byte swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 17 - LED Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 18 - Time Diagram of LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 19 - Configuration of Mirror Port for MDS213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 20 - Data Structure Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 21 - VLAN ID Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 22 - VLAN MAC Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 23 - Port Mapping Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 24 - Forwarding Port Mask Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 25 - Multicast Packet Forwarding Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 26 - XPIPE Interface - Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 27 - AC Characteristics - CPU BUS Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 28 - Local Memory Interface - Input Setup and Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 29 - Port Mirroring Interface - Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 30 - Port Mirroring Interface - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 31 - Reduce Media Independent Interface - Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 32 - Reduce Media Independent Interface - Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 33 - Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 34 - Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 35 - LED Interface - Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Zarlink Semiconductor Inc.
MDS213 List of Tables
Data Sheet
Table 1 - Type and Size of Memory Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 2 - Frame Buffer Memory Usage for Managed Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 3 - Frame Buffer Memory Usage For Unmanaged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 4 - Summary Description of the Source and Target End Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 5 - RMII Specification Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6 - Bootstrapping Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 7 - LED Signal Names and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 8 - MDS212 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 9 - Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 10 - Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 11 - AC Characteristics - XPipe Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 12 - AC Characteristics - CPU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 13 - AC Characteristics - Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 14 - AC Characteristics - Port Mirroring Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 15 - AC Characteristics - Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 16 - AC Characteristics - Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 17 - AC Characteristics - Physical Media Attachment Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 18 - AC Characteristics - LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Zarlink Semiconductor Inc.
MDS213
1.0
1
Data Sheet
16 17 18 19 20 21 22 23 24 25 26
Ball Signal Descriptions and Assignments
2 3 4 5 6 7 8 9 10 11 12 13 14 15
A AGND L_A2 L_A1 L_A1 L_A8 L_A4 X_D X_D X_D X_D X_D X_D X_D X_D X_DC X_DI X_DI X_DI X_DI X_DI X_DI X_DI X_DI P_CS P_RE P_GN 0 9 1 O29 O25 O20 O16 O13 O8 O5 O2 LKO 29 25 21 17 12 8 4 2 I# Q1 TC B Reser Rese L_A1 L_A1 L_A1 L_A5 X_D X_D X_D X_D X_D X_D X_D X_D X_FC X_DI X_DI X_DI X_DI X_DI X_DI X_DI X_DC Rese NC ved rved 8 4 0 O30 O26 O21 O18 O14 O10 O4 O3 O 28 23 20 16 11 7 3 LKI rved NC
C AVDD Rese Rese L_A1 L_A1 L_A6 X_D X_D X_D X_D X_D X_D X_D X_D X_DI X_DI X_DI X_DI X_DI X_DI X_DI X_DN Rese P_RE P_BR P_BL rved rved 7 3 O31 O28 O24 O19 O15 O12 O6 O1 31 27 22 18 14 10 6 I rved QC DY AST D E L_D4 L_D1 L_CL NC L_A1 L_A1 L_A7 L_A3 X_D X_D X_D X_D X_D X_DE X_DI X_DI X_DI X_DI X_DI X_DI X_DI X_FC P_IN P_RD P_RS P_A8 K 6 2 O27 O23 O17 O11 O7 NO 30 24 19 15 9 5 1 I T Y# T# L_D6 L_D5 L_D2 L_D0 GND L_A1 VCC L_A9 VDD _X_D VCC X_D GND X_D X_DI VCC X_DI VDD X_DI VCC P_G GND P_AD P_A1 P_CL P_A7 5 O22 O9 O0 26 13 0 NT1 S# 0 K P_R P_A9 P_A4 P_A3 P_A2 WC# VCC P_A6 P_D3 P_D3 P_D2 1 0 9 P_A5 P_A1 P_D2 P_D2 P_D2 8 6 4 VDD P_D2 P_D2 P_D2 P_D2 7 3 1 0 P_D2 P_D2 P_D1 P_D1 P_D1 5 2 9 8 6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC P_D1 P_D1 P_D1 P_D1 7 4 3 2 P_D1 P_D1 P_D1 P_D9 P_D8 5 0 1 VDD P_D7 P_D6 P_D4 P_D5 P_D0 T_D0 P_D1 P_D3 P_D2 T_D1 T_D4 T_D3 T_D2 T_D1 0 VCC T_D9 T_D7 T_D6 T_D5 T_D2 T_D1 T_D1 T_D1 T_D8 0 5 2 1 VDD T_D1 T_D1 T_D1 T_D1 9 6 4 3 PM_ T_D2 T_D2 T_D1 T_D1 DO[1] 5 1 8 7 VCC PM_ T_D2 T_D2 T_D2 DEN 4 3 2 O M12_ LE_# PM_ PM_ PM_ RXD5 SYN DI[1] DI[0] DENI CI
F L_D11 L_D1 L_D8 L_D3 T_M 0 ODE # G L_D1 L_D1 L_D1 L_D7 VCC 5 4 3 H J K L L_D2 L_D1 L_D1 L_D1 L_D9 0 8 6 2 L_D2 L_D2 L_D2 L_D1 VDD 4 3 1 7 L_D2 L_D2 L_D2 L_D2 L_D1 9 7 6 2 9 L_WE L_D3 L_D3 L_D2 VCC O# 1 0 8
M L_BW L_OE L_W L_OE L_D2 0# 0# E1# 1# 5 N L_BW L_AD L_B L_B S_CL 3# S# W2# W1# K P L_BW L_B L_B L_B VDD 5 W4 W7 W6 R T U V L_D3 L_D3 L_D3 L_D3 L_D3 3 4 6 5 2 L_D3 L_D3 L_D3 L_D4 VCC 7 8 9 1 L_D4 L_D4 L_D4 L_D4 L_D4 0 2 3 6 7 L_D4 L_D4 L_D4 L_D5 VDD 4 5 8 1
W L_D4 L_D5 L_D5 L_D5 L_D5 9 0 2 6 7 Y L_D5 L_D5 L_D5 L_D6 3 4 5 1 VCC
AA L_D5 L_D5 L_D6 M_CL M0_T 8 9 0 KI XD0
AB L_D6 L_D6 M0_T M0_C M2_L M3_ M5_L M6_T M8_T M9_T M10_ M11_ M12_ M_M LE_# LE_S PM_ 2 3 XEN RS_D GND NK VCC CRS VDD NK VCC XD1 XD0 GND XD1 VCC RXD1 VDD TXD0 VCC TXER GND DC CLK YNC DO[0] V _DV O O AC M0_L M0_T M0_R M1_T M2_T M2_ M3_T M4_L M4_ M5_T M6_T M7_L M7_CM8_R M9_T M10_ M10_ M11_ M12_ M12_ M12_ M12_ M12_ M_M LE_D LE_D NK XD1 XD1 XEN XD1 RXD XD1 NK RXD XD0 XEN NK RS_D XD1 XEN TXEN RXD0RXD1 TXD0 TXD3 TXD6 RXE RXD4 DIO I O 1 1 V R AD NC M0_R M1_T M2_T M2_C M3_T M4_T M4_ M5_T M5_ M6_C M7_T M7_RM8_C M9_T M9_R M10_ M11- M11_ M12_ M12_ M12_ M12_ M12_ M12_ M12_ XD0 XD1 XEN RS_D XD0 XEN CRS XD1 RXD RS_D XEN XD1 RS_D XD0 XD0 TXD0 TXEN RXD0 LNK TXD2 TXD7 RXD RXD3RXCLRXD0 V _DV 0 V V V K AE NC M1_L M1_R M2_T M3_L M3_ M4_T M4_ M5_ M6_L M6_R M7_T M8_L M8_T M9_L M9_R M10_ M11_ M11_ M12_ M12_ M12_ M12_ M12_ NC M12_ NK XD0 XD0 NK RXD XD1 RXD CRS NK XD1 XD1 NK XEN NK XD1 TXD1 LNK CRS_ TXCL TXD1 TXD5 TXEN RXD7 RXD1 1 0 _DV DV K AF M1_T M1_CM1_R M2_R M3_T M3_ M4_T M5_T M5_ M6_T M6_R M7_T M7_R M8_T M8_RM9_C M10_ M10_ M11_ M12_ M12_ M12_ GREF M12_ NC M12_ RXD2 XD0 RS_ XD1 XD0 XEN RXD XD0 XEN RXD XD0 XD0 XD0 XD0 XD1 XD0 RS_ LNK CRS_ TXD1 CRS COL TXD4 _CLK RXD6 0 1 DV DV DV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
VCC = 3.3VDC for I/O (16 balls) VDD = 2.5VDC for core logic (10 balls) GND = Digital Ground for both VCC and VDD (42 balls) AVDD = 2.5VDC for Analog PLL (1 ball) AGND = Isolated Analog Ground for AVDD (1 ball) NC = No Connection Reserved = Do Not Connect
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Zarlink Semiconductor Inc.
MDS213
1.1 Ball Signal Assignments
Ball No. D4 C3 A1 B1 C1 F5 C2 D3 E4 D2 E3 F4 D1 E2 E1 G4 F3 H5 F2 F1 H4 G3 G2 G1 H3 J4 H2 K5 H1 J3 K4 J2 Signal Name L_D24 Signal Name NC RESERVED AGND RESERVED AVDD T_MODE# RESERVED L_CLK L_D0 L_D1 L_D2 L_D3 L_D4 L_D5 L_D6 L_D7 L_D8 L_D9 L_D10 L_D11 L_D12 L_D13 L_D14 L_D15 L_D16 L_D17 L_D18 L_D19 L_D20 L_D21 L_D22 L_D23 L_D25 L_D27 L_D26 L_D28 L_D29 L_D30 L_D31 L_WE0# L_OEW# L_WE1# L_OE1# L_BW0# L_BW1# S_CLK L_BW2# L_BW3# L_ADS# L_BW4# L_BW5# L_BW6# L_BW7# L_D32 L_D33 L_D34 L_D35 L_D36 L_D37 L_D38 L_D39 L_D40 L_D41 L_D42 L_D43 Ball No. J1 M5 K2 K3 L4 K1 L3 L2 L1 M2 M3 M4 M1 N4 N5 N3 N1 N2 P2 P1 P4 P3 R5 R1 R2 R4 R3 T1 T2 T3 U1 T4 U2 U3 Signal Name L_D44 L_D45 L_D46 L_D47 L_D48 L_D49 L_D50 L_D51 L_D52 L_D53 L_D54 L_D55 L_D56 L_D57 L_D58 L_D59 L_D60 L_D61 L_D62 L_D63 M0_LNK M_CLKI M0_TXEN M0_TXD1 M0_TXD0 M0_CRS_DV M0_RXD1 M0_RXD0 NC NC M1_LNK M1_TXEN M1_TXD1 M1_TXD0
Data Sheet
Ball No. V1 V2 U4 U5 V3 W1 W2 V4 W3 Y1 Y2 Y3 W4 W5 AA1 AA2 AA3 Y4 AB1 AB2 AC1 AA4 AB3 AC2 AA5 AB4 AC3 AD2 AD1 AE1 AE2 AC4 AD3 AF1
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Zarlink Semiconductor Inc.
MDS213
Signal Name M1_CRS_DV M1_RXD1 M1_RXD0 M2_LNK M2_TXEN M2_TXD1 M2_TXD0 M2_CRS_DV M2_RXD1 M2_RXD0 M3_LNK M3_TXEN M3_TXD1 M3_TXD0 M3_CRS_DV M3_RXD1 M3_RXD0 M4_LNK M4_TXEN M4_TXD0 M4_TXD0 M4_CRS_DV M4_RXD1 M4_RXD0 M5_LNK M5_TXEN M5_TXD1 M5_TXD0 M5_CRS_DV M5_RXD1 M5_RXD0 M6_LNK M6_TXEN M6_TXD1 Ball No. AF2 AF3 AE3 AB6 AD4 AC5 AE4 AD5 AC6 AF4 AE5 AF5 AC7 AD6 AB8 AE6 AF6 AC8 AD7 AE7 AF7 AD8 AC9 AE8 AB10 AF8 AD9 AC10 AE9 AF9 AD10 AE10 AC11 AB12 Signal Name M6_TXD0 M6_CRS_DV M6_RXD1 M6_RXD0 M7_LNK M7_TXEN M7_TXD1 M7_TXD0 M7_CRS_DV M7_RXD1 M7_RXD0 M8_LNK M8_TXEN M8_TXD1 M8_TXD0 M8_CRS_DV M8_RXD1 M8_RXD0 M9_LNK M9_TXEN M9_TXD1 M9_TXD0 M9_CRS_DV M9_RXD1 M9_RXD0 M10_LNK M10_TXEN M10_TXD1 M10_TXD0 M10_CRS_DV M10_RXD1 M10_RXD0 M11_LNK M11_TXEN Ball No. AF10 AD11 AE11 AF11 AC12 AD12 AE12 AF12 AC13 AD13 AF13 AE13 AE14 AF14 AB13 AD14 AC14 AF15 AE15 AC15 AB15 AD15 AF16 AE16 AD16 AF17 AC16 AE17 AD17 AF18 AB17 AC17 AE18 AD18 Signal Name M11_TXD1 M11_TXD0 M11_CRS_DV M11_RXD1 M11_RXD0 M12_CRS
Data Sheet
Ball No. AF19 AB19 AE19 AC18 AD19 AF20 AE20 AD20 AC19 AF21 AE21 AD21 AC20 AF22 AE22 AF23 AC21 AD22 AE23 AB21 AC22 AD23 AE24 AF24 AF25 AE25 AA22 AC23 AD24 AF26 AE26 AD26 AD25
M12_TXCLK/GP_TXCL K M12_LNK/GP_LNK M12_TXD0/GP_TXD9 M12_COL/GP_RXCLK1 M12_TXD1/GP_TXD8 M12_TXD2/GP_TXD7 M12_TXD3/GP_TXD6 M12_TXD4/GP_TXD5 M12_TXD5/GP_TXD4 GREF_CLK M12_TXD6/GP_TXD3 M12_TXD7/GP_TXD2 M12_TX_EN/GP_TXD1 M12_TX_ER/GP_TXD0 M12_RX_ER/GP_RXD0 M12_RX_DV/GP_RXD1 M12_RXD7/GP_RXD2 M12_RXD6/GP_RXD3 NC NC M12_RXD5/GP_RXD4 M12_RXD4/GP_RXD5 M12_RXD3/GP_RXD6 M12_RXD2/GP_RXD7 M12_RXD1/GP_RXD8 M12_RXD0/GP_RXD9 M12_RXCLK/GP_ RSCLK0
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Zarlink Semiconductor Inc.
MDS213
Signal Name M_MDIO M_MDC LE_DI LE_CLKO LE_SYNCI LE_DO LE_SYNCO T_D31/PM_DO[1] T_D30/PM_DO[0] T_D29/PM_DENO T_D28/PM_DI[1] T_D27/PM_DI[0] T_D26/PM_DENI T_D25 T_D24 T_D23 T_D22 T_D21 T_D20 T_D19 T_D18 T_D17 T_D16 T_D15 T_D14 T_D13 T_D12 T_D11 T_D10 T_D9 T_D9 T_D8 T_D7 T_D6 Ball No. AC24 AB23 AC25 AB24 AA23 AC26 AB25 W22 AB26 Y23 AA24 AA25 AA26 W23 Y24 Y25 Y26 W24 U22 V23 W25 W26 V24 U23 V25 V26 U24 U25 R22 T23 T23 U26 T24 T25 Signal Name T_D5 T_D4/BS_RDYOP T_D3/BS_PSD T_D2/BS_SWM T_D1/BS_RW T_D0/BS_BMOD T_D0 P_D1 P_D2 P_D3 P_D4 P_D5 P_D6 P_D7 P_D8 P_D9 P_D10 P_D11 P_D12 P_D13 P_D14 P_D15 P_D16 P_D17 P_D18 P_D19 P_D20 P_D21 P_D22 P_D23 P_D24 P_D25 P_D26 P_D27 Ball No. T26 R23 R24 R25 R26 P23 P22 P24 P26 P25 N25 N26 N24 N23 M26 M25 M23 M24 L26 L25 L24 M22 K26 L23 K25 K24 J26 J25 K23 J24 H26 K22 H25 J23 Signal Name P_D28 P_D29 P_D30 P_D31 P_A1 P_A2 P_A3 P_A4 P_A5 P_A6 P_A7 P_CLK P_A8 P_A9 P_A10 P_RST# P_RWC# P_ADS# P_RDY# P_BRDY# P_BLAST# NC NC P_INT P_REQC P_GNTC P_REQ1 P_GNT1 P_CSI# RESERVED RESERVED X_FCI X_DCLKI X_DNI
Data Sheet
Ball No. H24 G26 G25 G24 H23 F26 F25 F24 H22 G23 E26 E25 D26 F23 E24 D25 F22 E23 D24 C25 C26 B26 B25 D23 C24 A26 A25 E21 A24 B24 C23 D22 B23 C22
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Zarlink Semiconductor Inc.
MDS213
Signal Name X_DI0 X_DI1 X_DI2 X_DI3 X_DI4 X_DI5 X_DI6 X_DI7 X_DI8 X_DI9 X_DI10 X_DI11 X_DI12 X_DI13 X_DI14 X_DI15 X_DI16 X_DI17 X_DI18 X_DI19 X_DI20 X_DI21 X_DI22 X_DI23 X_DI24 X_DI25 X_DI26 X_DI27 X_DI28 X_DI29 X_DI30 X_DI31 X_FCO X_DCLKO Ball No. E19 D21 A23 B22 A22 D20 C21 B21 A21 D19 C20 B20 A20 E17 C19 D18 B19 A19 C18 D17 B18 A18 C17 B17 D16 A17 E15 C16 B16 A16 D15 C15 B15 A15 Signal Name X_DENO X_DO0 X_DO1 X_DO2 X_DO3 X_DO4 X_DO5 X_DO6 X_DO7 X_DO8 X_DO9 X_DO10 X_DO11 X_DO12 X_DO13 X_DO14 X_DO15 X_DO16 X_DO17 X_DO18 X_DO19 X_DO20 X_DO21 X_DO22 X_DO23 X_DO24 X_DO25 X_DO26 X_DO27 X_DO28 X_DO29 X_DO30 X_DO31 L_A3 Ball No. D14 E14 C14 A14 B14 B13 A13 C13 D13 A12 E12 B12 D12 C12 A11 B11 C11 A10 D11 B10 C10 A9 B9 E10 D10 C9 A8 B8 D9 C8 A7 B7 C7 D8 L_A4 L_A5 L_A6 L_A7 L_A8 L_A9 L_A10 L_A11 L_A12 L_A13 L_A14 L_A15 L_A16 L_A17 L_A18 L_A19 L_A20 RESERVED VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Signal Name
Data Sheet
Ball No. A6 B6 C6 D7 A5 E8 B5 A4 D6 C5 B4 E6 D5 C4 B3 A3 A2 B2 E7 E11 E16 E20 G5 G22 L5 L22 T5 T22 Y5 Y22 AB7 AB11 AB16 AB20
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Zarlink Semiconductor Inc.
MDS213
Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. E9 E18 J5 J22 N22 P5 V5 V22 AB9 AB18 E5 E13 E22 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 P11 P12 P13 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Signal Name Ball No. P14 P15 P16 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15 T16 AB5 AB14 AB22
Data Sheet
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Zarlink Semiconductor Inc.
MDS213
2.0 Ball-Signal Descriptions
Data Sheet
The type of all pins is CMOS. All input pins are 5 Volt tolerance. All output pins are 3.3 CMOS drive. CPU Bus Interface Ball No(s) G24, G25, G26, H24, J23, H25, K22, H26. J24, K23, J25, J26, K24, K25, L23, K26, M22, L24, L25, L26, M24, M23, M25, M26, N23, N24, N26, N25, P25, P26, P24, P22 E24, F23, D26, E26, G23, H22, F24, F25, F26, H23 D25 F22 E23 D24 C25 C26 D23 E25 A24 C24 A26 A25 Symbol P_D[31:0] I/O I/O-TS, U Description Processor Data Bus Data Bit [31:0]
P_A[10:1]
Input /Out - U
Processor Address Bus Address Bit [10: 1]
P_RST# P_RWC# P_ADS# P_RDY# P_BRDY# P_BLAST# P_INT P_CLK P_CSI# P_REQC P_GNTC P_REQ1
In-ST Input/OutputTS, U Input/OutputTS, U Out-OD- TS, U Input- TS, U Input- TS, U Output Input Input- U Input Output Input/Output
Processor Bus - Master Reset Processor Bus - Read/Write Control Programmable polarity Processor Address Strobe Processor Bus - Data Ready Processor Bus - Burst Ready Processor Bus - Burst Last Processor Bus - Interrupt Request Programmable polarity Processor Bus - Bus Clock Chip Select Bus Request from CPU - Only using in debug mode when system is unmanaged. Bus Grant to CPU - Only using in debug mode when system in unmanaged. Bus Request from secondary MDS212 to primary MDS212. Only using in debug mode when system is unmanaged. Bus Grant to secondary MDS212 from primary MDS212. Only using in debug mode when system is unmanaged.
E21
P_GNT1
Input/Output
Note:
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Zarlink Semiconductor Inc.
MDS213
# = Active low signal Input = Input signal In-ST = Input signal with Schmitt-Trigger Output = Output signal (Tri-State driver) Out-OD = Output signal with Open-Drain driver I/O-TS = Input & Output signal with Tri-State driver I/O-OD = Input & Output signal with Open-Drain driver U = Internal weak pull-up TS = Tri-state ST = Schmitt Trigger
Data Sheet
Frame Buffer Interface Ball No(s) AB2, AB1, Y4, AA3, AA2, AA1, W5, W4, Y3, Y2, Y1, W3, V4, W2, W1, V3, U5, U4, V2, V1, U3, U2, T4, U1, T3, T2, T1, R4, R3, R2, R1, R5, L2, L3, K1, L4, K2, K3, M5, J1, J2, K4, J3, H1, K5, H2, J4, H3, G1, G2, G3, H4, F1, F2, H5, F3, G4, E1, E2, D1, F4, E3, D2, E4 A2, A3, B3, C4, D5, E6, B4, C5, D6, A4, B5, E8, A5, D7, C6, B6, A6, D8 D3 N2 P3, P4, P1, P2, N1, N3, N4, M1 M3, L1 M4, M2 Ball No(s) AB23 AB24 AA4 Symbol L_D[63:0] I/O-TS, U I/O Description Frame Buffer - Data Bit [63:0]
L_A[20:3]
Output
Frame Buffer - Address Bit [20:3]
L_CLK L_ADS# L_BW[7:0]# L_WE[1:0]# L_OE[1:0]#
Output Output Output Output Output
Frame Buffer Clock Frame Buffer Address Status Control Frame Buffer Individual Byte Write Enable [7:0] Frame Buffer Write Chip Select [1:0] Frame Buffer Read Chip Select [1:0]
RMII ETHERNET ACCESS PORTS [11:0] M_MDC M_MDIO M_CLKI Output I/O-TS Input MII Management Data Clock - (Common for all RMII Ports [11:0]) MII Management Data I/O - (Common for all RMII Ports [11:0]) Reference Input Clock
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Zarlink Semiconductor Inc.
MDS213
Frame Buffer Interface (continued) Ball No(s) AC18, AB17, AE16, AC14, AD13, AE11, AF9, AC9, AE6, AC6, AF3, AC3 AD19, AC17, AD16, AF15, AF13, AF11, AD10, AE8, AF6, AF4, AE3, AD2 AE19, AF18, AF16, AD14, AC13, AD11, AE9, AD8, AB8, AD5, AF2, AB4 AD18, AC16, AC15, AE14, AD12, AC11, AF8, AD7, AF5, AD4, AC4, AB3 AF19, AE17, AB15, AF14, AE12, AB12, AD9, AE7, AC7, AC5, AD3, AC2 AB19, AD17, AD15, AB13, AF12, AF10, AC10, AF7, AD6, AE4, AF1, AA5 AE18, AF17, AE15, AE13, AC12, AE10, AB10, AC8, AE5, AB6, AE2, AC1 Symbol M[11:0]_RXD [1] Input-U I/O Description Ports [11:0] - Receive Data Bit [1]
Data Sheet
M[11:0]_RXD [0]
Input-U
Ports [11:0] - Receive Data Bit [0]
M[11:0]_CRS _ DV
Input-U
Ports [11:0] - Carrier Sense and Receive Data Valid
M[11:0]_TXE N
Output
Ports [11:0] - Transmit Enable
M[11:0]_TXD[ 1]
Output
Ports [11:0] - Transmit Data Bit [1]
M[11:0]_TXD[ 0]
Output
Ports [11:0] - Transmit Data Bit [0]
M[11:0]_LNK
Input- ST, U
Ports [11:0] Link Status
GMII GIGABIT ETHERNET ACCESS PORT Ball No(s) AE24, AF24, AA22, AC23, AD24, AF26, AE26, AD26 AD23 AC22 Symbol M[12]_RXD[7: 0] M[12]_RX_DV M[12]_RX_ER Input-U I/O Description Port [12] -- Receive Data Bit [7:0]
Input-U Input- U
Port [12] -- Receive Data Valid Port [12] -- Receive Error
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Zarlink Semiconductor Inc.
MDS213
GMII GIGABIT ETHERNET ACCESS PORT Ball No(s) AF20 AF21 AD25 AD22, AC21, AE22, AF22, AC20, AD21, AE21, AC19 AE23 AB21 AE20 AD20 AF23 Ball No(s) AD26, AE26, AF26, AD24, AC23, AA22,AF24, AE24, AD23, AC22 AF21 AD25 AC19, AE21, AD21, AC20,. AF22, AE22, AC21, AD22, AE23, AB21 AE20 AD20 AF23 XPIPE INTERFACE Ball No(s) B23 C22 D22 Symbol X_DCLKI X_DENI X_FCI Input Input Input I/O Description XPipe Data Clock Input XPipe Data Enable Input XPipe Flow Control Input Symbol M[12]_CRS M[12]_COL M[12]_RXCLK M[12]_TXD[7: 0] Input- U Input- U Input- U Output I/O Description Port [12] - Carrier Sense Port [12] - Collision Detected Port [12] - Receive Clock
Data Sheet
Port [12] -- Transmit Data Bit [7:0]
M[12]_TX_EN M[12]_TX_ER M[12]_ TXCLK M[12]_LNK GREF_CLK
Output Output Output Input- ST, U Input- U
Port [12] -- Transmit Data Enable Port [12] -- Transmit Error Port [12] - Gigabit Transmit Clock Port [12]--:Link Status Port [12] - Gigabit Reference Clock
TBI GIGABIT ETHERNET ACCESS PORT [12] GP_RXD[9:0] Input- U Port [12] - TBI Receive Data Bit [9:0]
GP_RXCLK1 GP_RXCLK0 GP_TXD[9:0]
Input- U Input- U Output
Port [12] - TBI Receive Clock 1 Port [12] - TBI Receive Clock 0 Port [12] - TBI Transmit Data Bit [9:0]
GP_TXCLK GP_LNK GREF_CLK
Output Input- ST, U Input - U
Port [12] - TBI Gigabit Transmit Clock Port [12] - TBI Link Status Port [12] - TBI Gigabit Reference Clock
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Zarlink Semiconductor Inc.
MDS213
XPIPE INTERFACE Ball No(s) C15, D15, A16, B16, C16, E15, A17, D16, B17, C17, A18, B18, D17, C18, A19, B19, D18, C19, E17, A20, B20, C20, D19, A21, B21, C21, D20, A22, B22, A23, D21, E19 A15 B15 D14 C7, B7, A7, C8, D9, B8, A8, C9, D10, E10, B9, A9, C10, B10, D11, A10, C11, B11, A11, C12, D12, B12, E12, A12, D13, C13, A13, B13, B14, A14, C14, E14 PORT MIRRORING AA26 AA25, AA24 Y23 AB26, W22 PM_DENI PM_DI [1:0] PM_DENO PM_DO[1:0] Input- TS, U Input- TS, U Output Output Symbol X_DI[31:0] Input I/O Description XPipe Data Input Bits [31:0]
Data Sheet
X_DCLKO X_FCO X_DENO X_DO[31:0]
Output Output Output Output
XPipe Data Clock Output XPipe Control Output XPipe Data Enable Output XPipe Data Output Bit [31:0]
Port Mirroring Data Enable Input Port Mirroring Input Data Bit [1:0] Port Mirroring Data Enable Output Port Mirroring Output Data Bit [1:0]
TEST FACILITY (sharing pins with other functions and for Testing purpose only) F15 T_MODE# I/O-TS, U Test Pin - Set Mode upon Reset, and provides test status output.
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Zarlink Semiconductor Inc.
MDS213
XPIPE INTERFACE Ball No(s) W22, AB26, Y23, AA24, AA25, AA26, W23, Y24, Y25, Y26, W24, U22, V23, W25, W26, V24, U23, V25, V26, U24, U25, R22, T23, U26, T24, T25, T26, R23, R24, R25, R26, P23 LED INTERFACE AC25 AA23 AB24 AC26 AB25 LE_DI LE_SYNC# LE_CLKO LE_DO LE_SYNCO# Input- U Input- U Output Output Output LED Serial Data Input Stream LED Input Data Stream Symbol T_D[31:0] Output I/O Test Output Description
Data Sheet
LED Serial Interface Output Clock LED Serial Data Output Stream LED Output Data Stream
SYSTEM CLOCK, POWER AND GROUND PINS Ball No(s) N5 E9, E18, J5, J22, N22, P5, V5, V22, AB9, AB18 E7, E11, E16, E20, G22, L22, T22, Y22, AB20, AB16, AB11, AB7, Y5, T5, L5, G5 Symbol S_CLK VDD Input Power I/O Description System Clock at 100 MHz +2.5 Volt DC Supply
VCC
Power
+3.3 Volt DC Supply
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Zarlink Semiconductor Inc.
MDS213
SYSTEM CLOCK, POWER AND GROUND PINS Ball No(s) E5, E13, E22, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, AB5, AB14, AB22 C1, C1 A1, A1 BOOTSTRAP PINS P23 R26 BS_BMOD BS_RW Input Input CPU Bus mode Must be set to 0 Symbol VSS I/O Power Ground Ground Description
Data Sheet
AVDD[1:0] AVSS[1:0]
Analog Power Analog Ground
Used for the PLL Used for the PLL
CPU Read/Write Control Polarity Selection Default=1 0=R/W#; 1=W/R# Switch mode: Default=1 0=Managed mode 1= Unmanaged Primary Device Enable Pin Default=1 0=Secondary 1=Primary Option of merge the P_RDY# and P_BRDY# as one pin Default=1 0=Merged pin 1=Separated pins
R25 R24 R23
BS_SWM BS_PSD BS_RDYOP
Input Input Input
Note: # = Active low signal Input = Input signal In-ST = Input signal with Schmitt-Trigger Output = Output signal (Tri-State driver) Out-OD = Output signal with Open-Drain driver I/O-TS = Input & Output signal with Tri-State driver I/O-OD = Input & Output signal with Open-Drain driver U = Internal weak pull-up TS = Tri-state ST = Schmitt Trigger
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Zarlink Semiconductor Inc.
MDS213
3.0 The Media Access Control (MAC) and GIGABIT (GMAC)
Data Sheet
The MDS213 MAC/GMAC contains twelve Fast Ethernet MACs and one Gigabit Ethernet MAC, defined by the IEEE Standard 802.3 CSMA/CD. Each Fast Ethernet MAC is connected to a Physical Layer (PHY) via the Reduced Media Independent Interface (RMII), and the Gigabit Ethernet MAC is connected to a PHY via the Gigabit Media Independent Interface (GMII) or the Ten Bit Interface (TBI). The MAC/GMAC sublayer ("MAC/GMAC") consists of a Transmit and Receive section and is responsible for data encapsulation/ decapsulation. Data encapsulation/ decapsulation involves framing (frame alignment and frame synchronization), handling source and destination addresses, and detecting physical medium transmission errors. The MAC/GMAC also manages half-duplex collisions, including collision avoidance and contention resolution (collision handling). The MDS213 includes an optional MAC Control sublayer ("MAC Control") used for IEEE Flow Control functions. During frame transmission, the MAC transmit section encapsulates the data by prepending a preamble and a Start of Frame Delimiter (SFD), inserts a destination and source address, and appends the Frame Check Sequence (FCS) for error detection. In VLAN aware switches, the MAC/GMAC inserts, replaces, or removes VLAN Tags from these frame formats based on instructions from the Search Engine. When necessary, the MAC/GMAC regenerates the Frame Check Sequence and performs "padding" for frames less than 64 bytes. During frame reception, the MAC receive section verifies that the CRC is valid, de-serializes the data, and buffers the frame into the Receive FIFO. The MAC/GMAC then signals the Frame Engine, using Receive Direct Memory Access (RxDMA), that data is available in the FIFO and is ready for storage.
3.1
MAC/GMAC Configuration
MAC/GMAC operations are configured through the global Device Configuration Register (DCR2) and/or the MAC/GMAC Control and Configuration Registers (ECR0, ECR1), defined in the Register Definition Section of the MDS213 data sheet. The default settings for Autonegotiation, flow control, frame length, and duplex mode may be changed and configured by the user on a per-port basis, either in hardware or software.
3.2
The Inter-frame Gap
The Inter-frame Gap (IFG), defined as 96 bit times, is the interval between successive Ethernet frames for the MAC/GMAC. Depending on traffic conditions, the measurement reference for the IFG changes. If a frame is successfully transmitted without a collision, the IFG measurement starts from the de-assertion of the Transmit Enable (TXEN) signal. However, if a frame suffers a collision, the IFG measurement starts from the deassertion of the Carrier Sense (CRS) signal.
3.3
Ethernet Frame Limits
A legal Ethernet frame size, defined by the IEEE specification, must be between 64 and 1518 bytes, referring to the packet length on the wire. For transmitting or forwarding frames whose data lengths do not meet the minimum requirements, the MAC/GMAC appends extra bytes (padding) from the PAD field. Frames, longer than the maximum length may either be forwarded or discarded, depending on the register configuration. Although the MAC/GMAC may be configured to forward oversized frames in the Device Configuration Register (DCR2), the frame buffers' maximum size of 1536 bytes cannot be exceeded. For VLAN Aware systems, the maximum frame size is increased from 1518 bytes to 1522 bytes to accommodate the 4-byte VLAN Tag.
3.4
Collision Handling and Avoidance
In half duplex mode, if multiple stations on the same network attempt to transmit at the same time, interference could occur causing a collision. The MAC/GMAC monitors the Carrier Sense (CRS) signal to determine if the medium is available before attempting to transmit data. If the transmission medium is busy, the MAC/GMAC defers (delays) its own transmissions to decrease the load on the network. This is called collision avoidance.
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
If a collision occurs, after the first 64 bytes of data, the MAC/GMAC ceases data transmission and sends the jam sequence to notify all connected nodes of a collision. This jam sequence will persist for 32 bit times. The jam sequence is a 32 bit predetermined pattern used to notify other nodes that there is a collision on the network. If a collision occurs during preamble generation, or within the first 64 bytes, the transmitter waits until the preamble is completed and then "backs off" (that is, stops transmitting) for a specific period (defined by the IEEE 802.3 Binary Exponential Backoff Algorithm) before sending the jam sequence and rescheduling transmission. A frame with a size no less than 96 bits (64 bits of preamble and 32 bits of jam pattern), is sent to guarantee that the duration of the collision is long enough to be detected by the transmitting ports involved.
3.5
Auto-negotiation
The default value of the MDS213 MAC/GMAC enables Auto-negotiation. The default value is over written if the PHY lacks the ability to support Auto-negotiation, which is ascertained through its respective management interface, RMII/GMII. The Auto-negotiation process detects the different modes of operation (i.e. speed selection, duplex mode) supported by the system at the other end of the link segment. Upon power on/reset, the PHY generates a special sequence of fast link pulses (FLPs) to begin Auto-negotiation. The MDS213 MAC/GMAC, supporting Auto-negotiation, reads the results from status register in the PHY (10/100 mode) or in the PCS submodule (PCS Giga mode).
3.6
VLAN Support
Virtual Local Area Networks (VLANs) assemble a group of independent ports (and/or MAC addresses) to communicate as if they were on the same physical LAN segment, without being restricted by the physically connected hardware. The ports are logically grouped together by VLAN Identifiers (VLAN IDs). The MDS213 implements a MAC Address-based classification that associates each VLAN ID with its MAC address in the Switch Database Memory (SDM) for purposes of aging out, or replacing, old VLANs. The MDS213 MAC/GMAC recognizes VLAN-Tagged frame formats. During transmission, the MAC/GMAC inserts (or extracts) the 4-byte VLAN Tag and regenerates the Frame Check Sequence for the transmitted frame. VLAN support requires an increase in the maximum legal frame size, which is set in the Device Configuration Register (DCR2), from 1518 to 1522 bytes. During transmission, if the MAC/GMAC is required to remove the VLAN Tag from a 64-67 byte Rx frame, the MAC/GMAC will append extra bytes (pad) to form a 64 byte frame.
3.7
MAC Control Frames
MAC Control Frames, as defined by the IEEE, are used for specific control functions within the MAC Control sublayer "MAC Control." Similar to data frames, control frames are also encapsulated by the CSMA/CD MAC, meaning that they are prepended by a Preamble and Start of Frame delimiter and appended by a Frame Check Sequence. These frames may be distinguished from other MAC frames by their length/type field identifier (88.08h). The control functions are distinguished by an opcode contained in the first two bytes of the frame. Upon receipt, MAC control parses the incoming frame and determines, by looking at the opcode and the MAC address, whether it is destined for the MAC (a data frame) or for a specific function within MAC Control. After performing the specified functions, the MDS213 discards all MAC control frames it receives, regardless of the port configuration. These control frames are not forwarded to any other port and are not used to learn source addresses.
3.8
Flow Control
Flow control reduces the risk of data loss in the event a long burst of activity causes the MDS213 to saturate the buffer memory with backlogged frames. The MDS213 supports two types of Flow Control: Collision-based for halfduplex mode and IEEE 802.3x Flow Control for full duplex mode. In both cases, the MDS213 recognizes congestion by constantly monitoring available frame buffer memory. When the amount of free buffer space has been depleted, the MDS213 initiates the flow control mechanism appropriate to the current mode of operation. Setting the Flow Control (FC_Enable) bit in the MAC Port Configuration Register (ERC1) turns this operation on, thereby initiating PAUSE frames or applying backpressure flow control when necessary
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Zarlink Semiconductor Inc.
MDS213
3.8.1 Collision-Based Flow Control
Data Sheet
Collision-based Flow Control, also referred to as Backpressure Flow Control, inhibits frame reception for ports operating in half-duplex mode by "jamming" the link. When the free buffer space drops below a user-defined buffer memory threshold, the MDS213 sends a jam sequence to all non transmitting ports, after approximately eight bytes of payload data has been received, to generate a collision. The jam sequence is a predefined serial data stream sent to all ports to indicate that there has been a collision on the network. These ports will delay (defer) the transmission of data onto the network until the sequence has been completed.
3.8.2
IEEE 802.3x Flow Control
IEEE 802.3x Flow Control reduces network congestion on ports that are operating in full duplex mode using MAC Control PAUSE frames and is managed by the Flow Control Management Registers. The full-duplex PAUSE operation instructs the MAC to enable the reception of frames with a destination address equal to a globally assigned 48-bit reserved multicast address of 01-80-C2-00-00-01. These PAUSE frames are subsets of MAC Control frames with an opcode field of 0x0001 and are used by the MAC Control to request that the recipient stops transmitting non-control frames for a specific period. The PAUSE Timer is loaded from the PAUSE frame and is started upon the reception of a PAUSE frame. It will request a length of time for which it wishes to inhibit data frame transmission. In general, the IEEE standard allows pause frames longer than 64 bytes to be discarded or interpreted as valid. The MDS213 recognizes all MAC Control frames (PAUSE frames) between 64 and 1518 bytes long. Any PAUSE frames presented to the MAC outside of these parameters are discarded.
Preamble
SFD
DA
SA
DATA
PAD
FCS
Carrier Extension
Mll Frame Size: 512 bits Slot Time: 4096 bits FCS Coverage Late Collision Threshold: Slot Time - Header Size = 4032 bits GMAC Frame with Carrier Extension
Mac Frame with Extension InterFrame
Mac Frame
Inter Frame
Mac Frame
Burst Limit 65,536 bits Carrier Event Duration GMAC Frame Bursting
Figure 3 - Frame with Carrier Extension and Frame Bursting
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Zarlink Semiconductor Inc.
MDS213
3.9 Frame Bursting
Data Sheet
At speeds faster than 100Mbps and operating in half-duplex mode, the MAC/GMAC can transmit a series of frames without relinquishing control of the transmission medium. This is called Frame Bursting. Frame Bursting is utilized when a frame must be extended to the length of the slot time. With Frame bursting, only the first transmitted frame requires extension. Once a frame has been successfully transmitted, the Transmit section may submit consecutive frames onto the medium without contention, provided that no idle conditions exist between frames (e.g., no InterFrame Gap). The transmitting MAC/GMAC inserts extension bits, detected and extracted by the receiving MAC/GMAC, into the Inter-frame space interval. The MAC/GMAC may continuously initiate burst frame transmission up to the burst limit of 65,536 bits.
4.0
Frame Engine Description
The Frame Engine is the heart of the MDS213. It coordinates all data movements, ensuring fair allocation of the memory bandwidth and the XPipe bandwidth. When frame data is received from a MAC port, it is temporarily stored in the MAC Rx FIFO until the Frame Engine moves it to the chip's external memory one granule (128-byte-or-less fragment of frame data) at a time. The Frame Engine then issues the Search Engine a switching request that includes the source MAC address, the destination MAC address, and the VLAN tag. After the Search Engine has resolved the address, it transfers the information back to the Frame Engine via a switching response that includes the destination port and frame type (e.g. unicast or multicast). When the destination port is idle, the frame data is fetched from the memory and is written to the destination port's MAC Tx FIFO. However, when the destination port is busy transmitting another frame, the Frame Engine writes a transmission job that includes a frame handle for future identification. These transmission jobs are stored in the destination port's transmission scheduling queues (TxQ). There are four TxQs per port, one for each priority class. When the destination port is ready, the Frame Engine selects the head-of-line job from a TxQ. The frame, specified by the job, will be fetched from the memory and will be written to the MAC TxFIFO. For unicast frames, if the destination device is local (i.e., the destination port is located in the same device), the Frame Engine writes a job into the destination port's transmission scheduling queue (TxQ). The Transmit DMA (TxDMA) moves the frame data to the MAC Tx FIFO once the frame's transmission job is selected for transmission. If the destination device is remote (i.e., the destination port is located on another device, and can only be reached through the XPipe), all signaling between the two devices are sent as XPipe messages. The Frame Engine sends a scheduling request message via the XPipe to the destination port. This message asks the remote Frame Engine to write a job into the destination port's TxQ. When that job is selected, the remote Frame Engine sends a data request message via the XPipe to the local Frame Engine. Reception of a data request message triggers the forwarding engine module to forward the frame data to the destination port, one granule at a time through the XPipe until the end of file (EOF) safely arrives at the remote port's MAC TxFIFO. For multicast frames, the process is slightly different. The Frame Engine uses the VLAN index, which is part of the search result, to identify the destination ports. For local destination ports, the Frame Engine writes a job to each port's TxQ. When a transmission job is selected, the TxDMA moves data from the memory to the MAC Tx FIFO. Multicast frame data is sent multiple times, until all local destination ports' requests are satisfied. For a VLAN that includes remote destination ports, the multicast frame data is forwarded once through the XPipe and then stored in the remote device's memory. The remote Frame Engine processes this multicast frame as if it came from a local port. A frame is stored in a Frame Data Buffer (FDB) until it is transmitted. FDBs are external, located in a MDS213's frame buffer memory. To keep track of per-frame control information, the Frame Engine maintains one Frame Control Buffer (FCB) per frame. FCBs are internal. Since the Frame Engine does not access the external memory for frame control information, this conserves memory bandwidth for better performance.
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Data Sheet
As a frame lives through its lifecycle, its status is updated in the FCB. The FCB also contains vital frame information, such as destination port and length. There is a one-to-one correspondence between the FCB and the FDB: FCB#274 contains information about the frame stored in FDB#274. An FCB/FDB pair is called a "frame buffer," or simply a "buffer." The number 274 is called the handle or the buffer handle. The Frame Engine takes care of the distribution and the releasing of buffers. It also keeps buffer counters to ensure no port or single type of traffic occupies too many buffers. The receiving DMA (RxDMA) moves frame data from the MAC RxFIFO to the FDB. Before the RxDMA writes frame data into the FDB, it must obtain a free buffer handle from the buffer manager. A free buffer handle points to an empty or released frame buffer, ensuring that no stored frame data will get overwritten. After the EOF has been safely stored in the FDB, it writes the frame information to the FCB and issues a switching request to the Search Engine. If the frame is found to be bad (e.g., bad CRC), the buffer handle will be released and nothing will be written to the Search Engine or the FCB. This returns the buffer back to circulation and the frame is discarded. The RxDMA can fail to obtain a free buffer handle for two reasons. All buffers are currently occupied, or the received frame is a multicast frame and the multicast buffer quota is exhausted. In either case, the RxDMA will discard the frame, without getting a handle. If set, the register bit DCR2[26], IPMC, enables IP multicast privileges. If enabled, the RxDMA discards regular multicast frames if the multicast forwarding FIFOs occupancy exceeds the programmable threshold (see register MBCR[21:20], MCTH). An IP multicast frame is discarded only when the multicast frame's forwarding FIFO is full.
4.1
Transmission scheduling
There are four transmit scheduling queues (TxQ) per port, one for each priority. When a port is ready to transmit, when the previous frame finished transmitting, the port control module notifies the Frame Engine. The Frame Engine selects one TxQ out of the four priority queues, depending on the frame's arrival time and weighted round robin state (refer to the QoS chapter for more detail). It reads an entry from the selected transmission scheduling queue, and if the source port of the selected frame is local, a transmission request is issued to the local TxDMA module. If, on the other hand, the source port is remote, the data request message is forwarded across the XPipe and subsequently arrives at the forwarding engine. The four transmit scheduling queues per output port allows the Frame Engine to perform weighted round robin (WRR) to provide quality of service (QoS). The Search Engine classifies the frames into four internal priorities, Q0, Q1, Q2, and Q3, in decreasing priority. The 802.1p priority bits are mapped to the internal priorities by a programmable mapping, accessible via register AVTC. The user can program the queue weights via register AXSC, and thereby control the relative rates of the four internal-priority tagged frames. The maximum TxQ lengths are programmable from 128 entries to 1024 entries per queue. 52 TxQs are located in the external memory. The maximum queue lengths and the base memory addresses are accessible by the register group {CPUIRCMD, CPUIRDAT, CPUIRRDY}, under type QCNT.
4.2
Buffer Management
The buffer manager is responsible for the free handle allocation, buffer usage monitoring, buffer release and FCB access control. Free handles point to buffers that are not occupied by a frame. These free buffers can be allocated to a new frame received by the RxDMA. When the Frame Engine is done processing a frame, its handle is released to the free handle pool. The free handle pool must be initialized via the register group CPUIRCMD, CPUIRDAT, CPUIRRDY, type BMCT, before device operation. The Buffer Manager Control Table (BMCT) is the pool of free handles. At reset, the BMCT is empty. Prior to device operation, free handles must be written to the BMCT. The user must write the integers {0,1,2,3, ... K-1} to the BMCT one-at-a-time, where K is the maximum number of buffers. The value of K depends on the external memory size and partition, and it can be 128, 256, 512, or 1024. If all buffers are used, no more frames can enter the device. The Frame Engine keeps buffer counters that limit the number of buffers occupied by frames destined for each output port. If a buffer counter exceeds a programmable
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Data Sheet
threshold, its associated output port is "blacklisted." Entering frames destined to this output port are discarded, until the counter goes below the threshold. This threshold is programmed via registers BCT and BCHL. These counters prevent complete depletion of buffers due to an overloaded port, thus allow frames destined for non-congested ports to enter the system. This effectively avoids head-of-line blocking. The Frame Engine also keeps a buffer counter for multicast traffic types. The buffers occupied by incoming multicast frames are limited. This prevents multicast frames from blocking unicast ones from entering the system. The threshold for multicast traffic types is programmed via register MBCR.
5.0
5.1
Frame Buffer Memory
Frame Buffer Memory configuration
The MDS213 system utilizes external SRAM for its Frame Buffer Memory configuration, where the size of memory supported is 1/2 MB, 1MB and 2MB configurations. The following table shows four memory configuration examples for the MDS213 system. SRAM Type One Bank Address 64Kx32 128Kx32 L_A[18:3] L_A[19:3] Size 1/2MB 1MB Two Bank Address L_A[19:3] L_A[20:3] Size 1M 2M
Table 1 - Type and Size of Memory Chips The following figure shows the connections between the Frame Buffer Memory and the MDS213 for one-bank and two-bank memory configurations.
SRAM L_D[31:0] 64Kx32 L_A[18:3] L_A[18:3]
SRAMSRAM 64Kx32 64Kx32 L_A[18:3] L_A[18:3] CE MDS213
L_D[31:0] L_D[31:0] L_A[18:3] L_A[19] L_D[63:32] L_D[63:32] Two Bank 1M 64Kx32
CE
MDS213
SRAM L_D[63:32] 64Kx32 One Bank 0.5M 64Kx32
SRAM SRAM 64Kx32 64Kx32
SRAM L_D[31:0] 128Kx32 L_A[19:3] L_A[19:3]
SRAMSRAM 64Kx32 128Kx32 L_A[19:3] L_A[19:3] CE CE
L_D[31:0] L_D[31:0] L_A[19:3] L_A[20] L_D[63:32] L_D[63:32] Two Bank 1M 128Kx32
MDS213
MDS213
SRAM L_D[63:32] 128Kx32 One Bank 1.5M 128Kx32
SRAM SRAM 64Kx32 128Kx32
Figure 4 - Frame Buffer Memory Configuration
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5.2 Frame Buffer memory usage
Data Sheet
The MDS213 supports two switching modes: managed and unmanaged. The following tables describe Frame Buffer Memory usage for managed and unmanaged modes of operation, respectively. Description Frame Data Buffer (FDB) Transmission Queue CPU/HISC Mailing List VLAN Table VLAN MAC Table Unit Size 1.5 Kbytes 4 bytes x 128K to 4 bytes x 1K 32 Bytes to 64 Bytes (Programmable) 8 bytes x 4K 8 bytes to 32 bytes x 2K Unit Count 256 to 1K 52 (4 level priority) 128 to 1K Total Size 384 K bytes to 1.5M bytes 26 Kbytes to 208Kbytes (at 4 level priority) 4K bytes to 32 Kbytes (at 32 Bytes each) 32 Kbytes 16 Kbytes to 64 Kbytes Reference by FE1 FE1 CPU, HISC & SE1
1 1
HISC & SE1 HISC & SE1
Note: FE: Frame Engine, SE: Search Engine
Table 2 - Frame Buffer Memory Usage for Managed Mode Description Frame Data Buffer (FDB) Transmission Queue Unit Size 1.5 Kbytes 4 bytes x 128 to 4 bytes x 1K Unit Count 256 to 1K 52 (4 level priority) 13 (1 level priority) 128 to 1K Total Size 384 K bytes to 1.5M bytes 26 Kbytes to 208 Kbytes (at 4 level priority) Reference by FE FE
HISC Mailing List
32 Bytes to 64 Bytes (Programmable)
4K bytes to 32 Kbytes (at 32 Bytes each)
HISC & SE
Note: FE: Frame Engine, SE: Search Engine In unmanaged mode, the system does not support VLAN features. Thus, VLAN related tables are not required.
Table 3 - Frame Buffer Memory Usage For Unmanaged Mode
5.2.1
Memory Allocation of a Managed System
In a managed system, the Frame Buffer Memory is partitioned into five segments: Frame Data Buffers (FDBs), Transmission Queues, Mailing Lists, VLAN, and MCT VLAN Association Tables.
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63 FDB Frame Data Buffers (1.5KB x # of frame buffers) 0
Data Sheet
FDB block must start from 0
0
Transmission queues (4x13 =52 queues) (each entry = 1DW) (#entry of Queue = 128 to 1K) CPU/HISC Mailing List (#entry = 128 to 1K) (each mail entry=32 bytes to 64 bytes) VLAN Table (4k entry, 8B/entry) VLAN MAC Table (2k entry) (each entry=256, 128 or 64 bit) Byte Byte Byte ByteByte ByteByte Byte 7 6 5 4 3 2 1 0
Programmable Size
Programmable Size
32KB 16, 32 or 64KB
MAX 1/2MB, 1MB or 2MB
Figure 5 - Memory Map of Managed System
5.2.2
Frame Data Buffers
The Frame Data Buffers (FDBs) accommodates the incoming data frames and partitions them into data blocks, where each block occupies 1.5K bytes. The number of data blocks in FDB are configured by setting the value in the register FCBSL[9:0]. Since MDS213 supports up to 2M Bytes memory, the maximum number of data blocks is 1K. Note: The FDB must start at location 0.
5.2.3
Transmission Queues
The Transmission Queue controls the scheduling of the transmission ports, where each of these ports can support up to 4 priorities for each of the 13 ports of the MDS213. The number of priorities is programmable. Thus, the MDS213 may be configured for 13, 26, 39 or 52 Transmission Queues and may support 1, 2, 3 or 4 priority levels, respectively. The size of the Transmission Queue is 128, 256, 512, or 1024 entries and may be setup during the initialization phase. The Search Engine maintains the contents of each queue, where each queue consists of transmission priorities. Each double word (4-bytes) entry contains a FDB handle, which points to the corresponding frame in the buffer.
5.2.4
Mailing List
The Mailing List provides a communication channel between the HISC and CPU in managed mode. The size of a mail entry varies, ranging from 32 to 64 bytes, which is determined by the initialization setup. When the CPU or the HISC writes mail, the CPU/HISC can obtain a free mail by the register AFML that contains the addresses of free mail. Conversely, when the CPU or HISC reads its mail, the CPU/HISC accesses the mail by the register AMBX that contains the address of a CPU/HISC mail. All of the mail registers are maintained by the hardware.
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5.2.5 VLAN Table
Data Sheet
The VLAN Table associates the ports to their respective VLANs, using the VLAN ID. The table contains 4K VLAN entries, where each entry contains 8 bytes of information. The size of the VLAN Table is 32KB (4Kx8B). The base address of the VLAN Table is specified by the VIDB in the VTBP bit [5:0]. Note: The VLAN Table must be located at the 32K boundary.
5.2.6
VLAN MAC Association Table
The VLAN MAC Table (VLAN MCT) associates each port's MAC address with its respective VLAN. The Table comprises of 2048 entries, one entry per MAC address. Each VLAN MAC entry is mapped to each bit associated with a VLAN specified by the VLAN Index. The size of the Table is defined by two bits in the VTBP register and depends on the system configuration (e.g. the number of VLANs supported in the system). Each entry may consist of 256, 128 or 64 bits (one bit per VLAN). The total size of the VLAN MAC Table may be 16, 32 or 64KB. The VMACB field in the register VTBP specifies the base address. Note: The VLAN MAC Table must be located at the 16K boundary.
5.2.7
Unmanaged System memory allocation
Since an unmanaged system does not support VLAN operation, the VLAN and VLAN MAC tables are not required. Only the Frame Data Buffers, Transmission Queues, and HISC Mailing Lists are allocated in system memory.
63 0 0 FDB Frame Data Buffers (1.5KB x # of frame buffers)
FDB block must start from 0
Transmission queues (4x13 =52 queues) (each entry = 1DW) (#entry of Queue = 128 to 1K) HISC Mailing List (#entry = 128 to 1K) (each mail entry=32 bytes to 64 bytes) Byte Byte Byte ByteByte ByteByte Byte 7 6 5 4 3 2 1 0
Programmable Size
Programmable Size
MAX 1/2MB, 1MB or 2MB
Figure 6 - Memory Map of an Unmanaged System
5.3 5.3.1
The Frame Memory Interface Local memory interface
Each frame within the MDS213 is allocated its own buffer memory. The primary function of the Frame Buffer Memory is to provide a temporary buffering space for both received and transmitted frames, as well as frames waiting in the transmission queue. The actual usage depends on the frame type to be transmitted, either unicast or multicast and the relationship between the source and destination ports. The buffer memory also, contains other control structures including stacks, queues, other control tables. The buffer memory may be configured for 128K,
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Data Sheet
256K, 512K, 1024K Bytes depending on the application of the system designer. The MDS213 local memory interface supports up to 2M bytes of SRAM.
6.0
Search Engine
The Search Engine is responsible for determining the destination information for all packet traffic that enters the MDS213. The results from all address or VLAN searches are passed to the Frame Engine to be forwarded, or on to the HISC block for further processing. The result messages to either the Frame Engine or the HISC provide all the needed information to allow the destination block to process the packet. The Search Engine has been optimized for high throughput searching, utilizing the integrated Switch Database Memory (SDM). The internal SDM contains up to 2k MAC Control Table (MCT) entries. These MCT entries are searched utilizing one of four Hashing algorithms that can be selected. This provides the capability of changing the search hashing to optimize the hash tables based on the traffic patterns in a given network. For example, if a company gets all their Network Interface Cards (NIC) from one vendor, then the source and destination MAC addresses will have common fields. This can lead to inefficient search hashing. With 4 different hash selections that utilize different parts of the address fields, and can be 8, 9, or 10 bits in length, the hashing algorithm that works best for a user's network can be selected (by testing each hash algorithm).
Layer 1
Preamble
SFD
DATA
FCS
Packet
Layer 2
ENET 2 Header
Destination MAC Address Destination MAC Address Source MAC Address Source MAC Address VLAN Tag 0x800 Ver IHL Identifier Time to Live Protocol Typ of Serv Fig Total Length Fragment Offset Header Checksum 64 Bytes
Layer 3
IP Header
IP Source Address IP Destination Address Options + Padding Source Port # Destination Port # Sequence Number Acknowledgement Number Offset Reserved U A P R S F Checksum Options + Padding Data . . . Window Urgent Pointer
Layer 4
TCP/IP Header
Figure 7 - Typical Packet Header Information The search process begins when the Frame Engine transfers the first 64 bytes of a packet header to the Search Engine. These bytes are parsed to extract the information needed to perform the search for the MCT entries that match the source and destination MAC address, generate the search hash keys, lookup VLAN membership, and other packet status information.
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MDS213
6.1 Layer 2 Search Process
Data Sheet
When the MDS213 is in either a "forwarding" state (able to forward packets) or a "learning" state (able to learn new addresses), the Search Engine is capable of performing address searches. The search process begins when packet header information is transferred to the Search Engine from the Frame Engine. The Search Engine first checks to determine if the MDS213 is configured to support Virtual Local Area Networks (VLAN). If VLANs are enabled, the Search Engine will search for both the destination MAC address, to get destination resolution information, and the source MAC address, to get the port's VLAN membership and verify the validity of the port's VLAN membership. If VLANs are disabled, the Search Engine will search for the destination and source MAC addresses but will not do a VLAN table check.
6.1.1
VLAN Unaware
When VLANs are not enabled or configured, the Search Engine will search the internal switch database memory for an MCT that matches the destination MAC address. When a match is found, the Search Engine will check to ensure that the destination address is not to be filtered before sending a search result message back to the Frame Engine to start the packet forwarding process. At the same time, a search for the MCT that matches the source MAC address is also performed. If no match is found for the source address, then the source MAC address needs to be learned.
6.1.2
VLAN Aware
When VLANs are enabled and configured, the Search Engine will begin searching for the destination MCT and the source MCT. If a matching MCT is found for the source address, then no learning is required, and the Search Engine will check the VLAN membership of the source port. If the source port is a member of the VLAN, and the destination port is also a member of the VLAN, then a normal response message will be passed to the Frame Engine. If the source port is not a valid member of the VLAN, or the destination port is not a member of the VLAN, then the Search Engine will decide to forward the packet or drop the packet depending upon a user defined configuration. Then it will send a message to the HISC to allow the HISC to resolve the issue.
6.2
Address and VLAN learning
Address learning can be performed by either the HISC or the Search Engine and can be enabled or disabled. The global learning control is set in the Device Configuration Register (DCR2). The Global Learning Disable (GLN) bit controls whether learning is active or disabled, and can be set during initial power up configuration, or by an external CPU before it begins modifying the SDM. It is necessary for an external CPU to disable learning before updating or modifying MCT entries. This prevents the internal learning process from modifying MCT entries without the CPU's knowledge. When learning is globally enabled, by the Search Engine not finding a match to a source address search, it can create a new MCT with the necessary information, and then notify the HISC that a new address has been learned. If the Search Engine request queue becomes 3/4th full, the Search Engine will ignore address learning until the request queue is less full. In that case, packets are forwarded as usual, and a message is sent to the HISC requesting that the HISC learn the new address. If the Search Engine request queue is too full, and the HISC request queue is full, then no learning will take place. When two MDS213 chips are connected, and configured to operate with synchronized MCT entries, the HISC processor has the ability to send a request to the Search Engine, instructing it to learn a new address received from the other MDS213. The HISC processor can also use this method to make simple edits to the MCT entries for port changes (i.e. source MAC address is now connected to a different port on the MDS213).
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6.3 Flooding and Packet Control
Data Sheet
Packets, for which there are no matching destination MCT entries, are by default flooded to all output ports. This can result in broadcast storms and cause the number of flooded packets to increase rapidly. The MDS213 provides the user a means for setting a level of flooding, by providing a Flooding Control Register (FCR). The FCR allows the user to define a time base (100us to 12.8ms) during which packet flooding at each output port will be counted. Three separate flood control fields allow the user to specify flooding limits for: * * * Unicast to Multicast (flooded) packets per source port Unicast to CPU packets per chip Multicast to CPU packets per chip
During the time base period, three separate counters at each port count the number of packets meeting the flood control types. Once a counter exceeds the allowed quantity, the Search Engine will then discard the packet and any other packets of that type that enter the port during the remainder of the time base period. When the time base period is completed, the three flood counters at each port are reset, and the counting process starts over. The flooding control register is global for setting the limits on all register ports, but the individual ports have separate counters to keep track of the number of flooded.
6.4
Packet Filtering
Packet filtering occurs during the address search phase. For static source or destination MAC address filtering, there is a corresponding bit in the MCT entry that tells the Search Engine that the source or destination packet is to be filtered. When a match is found to a destination MAC address search, the "Destination Filter" (D) field in the MCT is checked to determine if the destination address is to be filtered. If "D" is asserted, the Search Engine discards the packet by sending a message to the Frame Engine telling it to release the Frame Control Buffer (FCB) where the packet has been stored in the frame buffer memory. The packet thereby deleted from memory. When a match is found to a source MAC address search, the "Source Filter" (S) field in the MCT is checked to determine if the source address is to be filtered. If "S" is asserted, then the Search Engine discards the packet by sending a message to the Frame Engine telling it to release the FCB for the packet.
6.5
Address Aging
Entries in the MCT database are removed if they have not been used within a user selectable time frame. This aging process is handled by inspecting a single MCT entry during each clock period. If the entry is valid and subject to aging, an aging flag in the MCT entry is cleared. If the aging flag is already set to zero during the inspection, an aging message is sent to the HISC processor to delete and free up the aged MCT entry. Each time an MCT entry is matched by way of a Search Engine, source search process, the aging flag is asserted to restart the aging process for that entry. Some entries may be static and not subject to aging. These MCT entries have a status field that identifies them as being static, and will therefore always have their aging flag asserted. The network manager, using Zarlink Management software, establishes static entries during a switch configuration session.
6.6
IP Multicast
The Search Engine supports the ability of the MDS213 to provide IP Multicast by identifying Internet Group Multicast Protocol (IGMP) packets when parsing the packet header information provided by the Frame Engine. IGMP packets are identified when the destination MAC address is 01-00-5E-xx-xx-xx, the Protocol field has the value of 2, and the source IP address is 224.0.0.x.
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Data Sheet
When an IGMP packet is identified, the Search Engine searches for the source address MCT entry, and then passes a message to the HISC to allow it to setup or tear down the IP Multicast session. IP Multicast sessions are treated as VLANs and use one of the 256 regular VLAN entries.
7.0
7.1
The High Density Instruction Set Computer (HISC)
Description
The High Density Instruction Set CPU (HISC) is specifically designed to implement highly efficient management functions for the MDS213 switching hardware, minimizing the management activity intervention during frame processing. The HISC services management requests based on an event-driven approach. Management requests can be generated from either the management CPU or the switching hardware. The HISC is also designed with a powerful instruction set and dedicated hardware interfaces for packet processing and transmission to provide high performance packet transfers between the CPU interface and the switching hardware.
7.2
HISC architecture
The HISC is designed with an advanced pipeline architecture that combines the advantages of both RISC and VLIW architectures. The HISC core combines a rich instruction set with 88 general-purpose registers and support for multiple-way jump. The 88 registers are divided into three parts, eight common general-purpose registers and two banks of 40 registers for two different task contexts. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction execution. Each HISC instruction may have up to three sub-instructions, which can be executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than a CISC processor or up to three times faster than a RISC processor. For a MDS213 running at 100MHz, the HISC can produce up to 300MIPs processing power.
7.3
HISC Operations
With an event-driven operation model, upon the request from either the Search Engine or external management CPU, the HISC dynamically manages and maintains the Switch Database including MAC address entries, VLAN and MAC-VLAN Association Tables. The HISC also provides an external management CPU a high-speed data communication interfaces, so management packets can be transmitted to or received from the network. In general, the service request is received from one of four different sources: * * * * Messages from the management CPU Requests from the switching hardware (Search Engine) Real time clock Interrupts to the management CPU
The HISC performs the following major operations: * * * * Resource initialization Resource management Switching database management Send and receive frames for management CPU
7.3.1
Resource Initialization
The HISC initializes all internal data structures including the mail box and switching database data structures, which are used by the management CPU, HISC and switching hardware.
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7.3.2 Resource Management
Data Sheet
The HISC can enforce a replacement policy when the number of free data structure for new MAC address entries is lower than the predefined threshold.
7.3.3
Switching Database Management
One of the major management tasks required of the HISC is to create, delete, and modify MAC address entries upon requests from the Search Engine or management CPU. Generally, the Search Engine performs the learning of new MAC addresses identified in the packet streams. For a single MDS213 system, the HISC simply informs the management CPU regarding the newly learned MAC addresses. The HISC may also create, delete, or modify the MAC address entries based on the requests from the management CPU. For a multi-MDS system, the HISC is response for synchronizing the switching databases. In addition to the MAC address entries, the HISC also maintains the following database information required for switching: * * * Create, delete and modify VLAN table in the switching database. Create, delete and modify MAC VLAN table in the switching database. Create, delete and modify IP Multicast entries in the switching database.
7.3.4
Send and Receive Frames for Management CPU
The HISC delivers BDPU, SNMP and other frames to and from the management CPU. In unmanaged mode, the HISC also responds to interrupts destined to the management CPU.
7.3.5
Communication Between HISC and Switching Hardware
High-speed communication channels are required to provide fast message deliveries between the HISC and switching hardware. Two high-performance FIFOs provide the required communication channels. They are between the HISC and the Frame Engine, and between the HISC and Search Engine.
7.3.6
Communication Between Search Engine and HISC
The first high-speed FIFO is used by the Search Engine to send messages, management requests or received packets, to the HISC. Whenever a message is sent to the FIFO, the HISC is notified of the new event. Each message may contain up to two command codes, processed by the HISC sequentially. The HISC can also request from the Search Engine to do operations such as search or learn via a HISC I/O interface. After processing the requests, the Search Engine then sends the response back to the HISC via the FIFO.
7.3.7
Communication Between HISC and Frame Engine
The second high-speed FIFO is used by the HISC for sending data transfer requests to the Frame Engine. Whenever a packet-forwarding request is received from the management CPU, the HISC forwards the request to the Frame Engine via the FIFO. To alleviate the workload of the management CPU, certain management packets can be processed by the HISC, and then forwarded to the Frame Engine for transmission via the FIFO.
7.4
Communication Between Management CPU and HISC
The HISC serves as an intermediary communication channel between the switching hardware and the external management CPU. There are two communication mechanisms provided for messages exchanged between the management CPU and HISC.
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7.4.1 CPU-HISC Communication Using Queues
Data Sheet
The first communication mechanism is a pair of Input and Output Queues between HISC and management CPU. The management CPU input/output queue is a very efficient mechanism for a single 32-bit data exchange between the HISC and management CPU. In general, a management frame, i.e., Bridged Data Protocol Units (BDPU), is forwarded directly from the HISC to the management CPU via the CPU Output Queue. Small management requests, less than 24 bits, are delivered to the HISC via the CPU Input Queue.
7.4.2
Mailbox
The second communication mechanism is a hardware mailbox that can support variable size messages, exchanged between the management CPU and the HISC. A major use of the mailbox is to exchange information required for updating the switching database.
7.4.3
CPU-HISC MAIL
When the management CPU sends a mail message to the HISC, the CPU acquires an address of a free mail from the free mail list (via register AFML). It then writes the mail content to the given memory address. Afterward, it sends the mail to the HISC via the Mailbox Access (AMBX) Register. Whenever a management mail message is received, an event is generated to inform the HISC to process the mail message.
7.4.4
HISC-CPU Mail
When a mail message arrives from the HISC, the mailbox hardware sends an interrupt, namely "Mail Arrive" (MAIL_ARR) to the CPU. The CPU can then access the mail via the Mailbox Access Register (AMBX). At this point, the CPU reads the mail handle and retrieves the contents of the mail from the AMBX Register.
8.0
The XPipe
The XPipe provides a high-speed link between systems utilizing two MDS213 devices. The XPipe incorporates a 32-bit-wide data pipe, with a high-speed point-to-point connections, and a full-duplex interface between devices. While operating at a 100MHz, this interface can provide 3.2G bits per second (Gbps) of bandwidth per pipe in both directions.
8.1
XPipe Connection
Transmit FIFO
X_DO[31:0] X_DCLKO X_DENO X_FCI
X_DI[31:0] X_DCLKI X_DENI X_FCO
Receive FIFO
Source
Xmit Ctrl
Rcvd Ctrl
Target
Receive FIFO
X_DI[31:0] X_DCLKI X_DENI X_FCO
X_DO[31:0] X_DCLKO X_DENO X_FCI
Transmit FIFO
Target
Recd Ctrl
Xmit Ctrl Source
MDS213
MDS213
Figure 8 - XPipe System Block Diagram for the MDS213
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
The XPipe interface employs 32 data signals and three control signals for each direction. The pin connections between two MDS213 devices are depicted in Figure 8. These 32 data signals form a 32-bit-wide transmission data pipe that carries XpressFlow messages to and from the devices. The direction of all signals are from the source to the target device, except for the flow control signal, which sends messages in the opposite direction; from the target to the source. The three control signals consist of: a Transmit Clock signal, a Transmit Data Enable signal, and a Flow Control signal. The Transmit Clock signal (X_DCLKO), provides a synchronous clock to sample the data signals at the target device. The source device provides the Transmit Data Enable signal (X_DENO) that envelops an entire XPipe message (including the Header and the Payload) and is used to identify the message boundary from the received data stream. The timing relationship between the data, clock, and data enable signals are described in the XPipe Timing (Section 10.2). The Flow Control signal (X_FC) monitors the state of the receiving queue at the target end to prevent XPipe message loss. When the target end does not have enough space to accommodate an entire XPipe message, the target device sends a XOFF signal by driving the X_FCO signal to LOW. The source device will stop further transmission until the X_FCI signal asserts the XON state, which is an active HIGH (Refer to Table 4). Signal Name Description Source End X_DO[31:0] X_DCLKO X_DENO X_FCI Target End X_DI[31:0] X_DCLKI X_DENI X_FCO 32-bit-wide Transmit Data Bus - Includes a XPipe Message Header and follows by the data payload Transmit Clock - Synchronous data clock provided by the source end Transmit Data Enable - Provided by the source end to envelop the entire XPipe message Flow Control Signal- A flow control pin from the target end to signal the source end to active XON/XOFF.
Table 4 - Summary Description of the Source and Target End Signals The XPipe Message Header provides the payload size, type of message, routing information, and control information for the XPipe incoming message. The routing information includes the device ID and port ID. The header size is dependent upon the message types and may be 2 to 4 words in length.
2-4 Words Header XpipeFlow Message Header
0-64 Words Payload Data Payload
Figure 9 - XPipe Message Header
8.2
XPipe Timing
The source device generates the X_CLKO signal to provide a synchronous transmit data clock. The Receiver will then sample the data on the falling (negative) edge of the clock, as shown in Figure 10. To identify the boundary between the XPipe messages and the data stream, the source device uses the X_DENO signal to envelop the entire XPipe message. That is, a rising (positive) edge at the beginning of the first double word
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
(4 bytes) and a falling (negative) edge at the beginning of the last double word of an XPipe message as shown in Figure 10. Note: The negative edge does not occur at the end of the last double word, but instead, at the beginning of the last double word. This allows XPipe messages to be sent consecutively (back-to-back).
.
Cycle #1 Cycle #2 Cycle #3 Cycle #4 X_CLKI/O
Cycle #5
Cycle #6
.........
Last Cycle
Idle
X_DENI/O
*1
X_DI/O[31:0]
D Word 0
D Word 1
D Word 2
D Word 3
.........
.........
.........
D Word N
Note 1: Positive edge at the beginning of the first Double Word. Negative edge at the beginning of the last Double Word.
Figure 10 - Basic Timing Diagram of XPipe
9.0
Physical Layer (PHY) Interface
The Physical Layer Interface is designed to interface Zarlink chipsets to a variety of Physical Layer devices. Reduced Media Independent Interface (RMII) is used for 10/100 interfaces, while Gigabit connections can use either Gigabit Media Independent Interfaces (GMII) or Ten Bit Interface (TBI). The chip ball names for the MAC use M as the first letter of the name, followed by their pin number, and then their function. For example, M1_RXD0 refers to Mac port 1, receive data 0 of the receive data pair.
9.1
Reduced MII (RMII)
The MDS213 implements the Reduced Media Independent Interface (RMII) signals, REF_CLK, CRS_DV, RXD [1:0], TX_EN, and TXD [1:0], defined in Section 5 of the RMII Consortium Specification. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u [2] MII interface. Under IEEE 802.3u [2] an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase. Zarlink MDS213 offer 12 or 24 ports, in one or two devices respectively. At 6 pins per port and 1 pin per switch ASIC, the RMII specification saves 119 pins plus the extra power and ground pins to support those additional pins for a 12 port switch ASIC. Architecturally, the RMII specification provides for an additional reconciliation layer on either side of the MII but can be implemented in the absence of an MII. The management interface (MDIO/MDC) is assumed to be identical to that defined in IEEE 802.3u [2]. The RMII supports both 10 and 100Mbps data rates across a two bit Transmit Data (TXD) path and a two bit Receive Data (RXD) path. The RMII uses a single synchronous clock reference sourced from the Media Access Controller (MAC), or an external clock source, to the Physical Layer (PHY). Doubling the clock frequency to 50 MHz allows a reduction of required data and control signals, thereby providing a low cost alternative to the IEEE Std 802.3u Media Independent Interface (MII). The RMII functions to make the differences between copper and optical PHYs transparent to the MAC sublayer. The RMII specification has the following characteristics: * * It is capable of supporting 10Mbps and 100Mbps data rates A single clock reference is sourced from the MAC to PHY (or from an external source)
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Zarlink Semiconductor Inc.
MDS213
* * It provides independent 2 bit wide (di-bit) transmit and receive data paths It uses TTL signal levels, compatible with common digital CMOS ASIC processes.
Data Sheet
RMII Specification Signals Direction (with respect of the PHY) Input or Output Direction (with respect to the MAC) Synchronous clock reference for receive, transmit and control interface Carrier Sense/Receive Data Valid Receive Data Transmit Enable Transmit Data Receive Error
Signal Name REF_CLK
M[0:11]_CRS_DV M[0:11]_RXD[1:0] M[0:11]_TX_EN M[0:11]_TXD[1:0] M[0:11]_RX_ER
Input Input Output Output Input (Not required)
Table 5 - RMII Specification Signals
9.2
The Gigabit Media Independent Interface (GMII)
The GMII supports the 1000Mbps full-duplex operations of the MDS213, based on the Media Independent Interface (MII) defined by IEEE Std 802.3 (Clause 22). The GMII retains the names and functions of most of the MII signals, but defines valid signal combinations for 1000Mbps operations. The GMII transfers data in each direction for the Data [7:0], Delimiter, Error, and Clock signals. The GMII implementation extends the Transmit Data (TXD) and Receive Data (RXD) signals of the MII from four bits wide to eight bits wide and synchronizes the data and the delimiters using a Gigabit Transmit Clock (GTX_CLK) instead of the MIIs' Transmit Clock (TX_CLK).
9.2.1
The MII Management Interface
The GMII uses the MII Management Interface is used to control and gather status information from the Gigabit Physical Layer (PHY) to configure MDS213 operations using Auto-negotiation. The management interface consists of a pair of signals, called the M_MDIO and M_MDC management pins.
9.2.2
MII Command and Status Registers
The MDS213 utilizes the MII Command and Status registers defined in the 10/100Mbps Specification and additional extended registers to support Auto-negotiation (IEEE Std 802.3, Clause 37). The commonality of the MII management registers will allow the MDS213 to determine the capabilities supported by the PHY and to implement such functions as "Start of Frame" and "Determine PHY Address."
9.3
The Physical Coding Sublayer with Ten Bit Interface (TBI):
Zarlink MDS213 includes the Physical Coding Sublayer (PCS) block. It performs 8B/10B conversion between GMII and Ten Bit Interface (TBI). The Collision Detect (COL) and Carry Sense (CRS) signals are generated from PCS to GMII internally when using TBI interface PHY. The PCS block also includes an Auto Negotiation function. The PCS block can be disabled by using the Device Configuration Register (DCR2) when GMII interface PHY is used.
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Zarlink Semiconductor Inc.
MDS213
10.0 The Control Bus
Data Sheet
The CPU Interface, or Control Bus, provides the communication path between the system CPU and all other key components within the MDS213 (i.e. the HISC). It operates in two modes: managed mode, where it utilizes an external CPU, and unmanaged mode, where an external CPU does not exist. In Managed mode, the CPU Interface provides the communication path between the systems' external CPU and the HISC, Frame Buffer Memory (SRAM) or another MDS213. See Figure 11.
Control Bus
MDS213
MDS213 CPU
Flash Memory
Figure 11 - CPU Interface Configuration in Managed Mode In unmanaged mode, the CPU Interface provides the communication path between the Switch Devices and Flash Memory, and between any two MDS213 Switches. See Figure 12.
Control Bus
Primary DEV MDS213 Arbitrator
Secondary DEV MDS213 Flash Memory
Figure 12 - Control Bus Configuration in Unmanaged Mode
10.1
External CPU Support
The control bus comprises of a 32-bit wide CPU bus and supports Big and Little Endian CPU byte ordering. The standard microprocessors supported include: * * * * Intel 486 CPUs Motorola MPC860 and 801 CPUs Intel i960Jx CPU MIPS processor with minimum conversion
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Zarlink Semiconductor Inc.
MDS213
10.1.1 Power On/Reset Configuration
Data Sheet
On power-up, the following five Bootstrap bits, of Table 6, are used: Name BS_BMOD BS_RW BS_SWM BS_PSD Default 1 1 1 1 Bus Mode Must be 0 Selects R/W Control polarity 0=R/W# 1=W/R# Switch Mode (only in Managed Mode) 0=Managed Mode 1=Unmanaged Mode Primary Device Enable (only in Unmanaged Mode) 0=Secondary Mode 1=Primary Mode (The arbiter is activated in the chip with Primary Device.) Option of merger the P_RDY# and P_BRDY# 0=merged P_RDY# and P_BRDY# pin 1=Separated P_RDY# and P_BRDY# pins Table 6 - Bootstrapping Options Functional Description
BS_RDYOP
1
10.1.2
CPU Bus Clock Interface
The CPU Interface allows the CPU bus clock to operate at clock rates different from the system clock rate. The CPU Bus Clock rate is always less than or equal to the System Clock rate.
10.1.3
Address And Data Buses
The CPU Interface provides separate, non-multiplexed address and data buses. The data bus is a synchronous, 32-bit bus that can receive 16 or 32-bit wide data. The Flash memory uses a 16-bit data bus. The data bus supports 32 bit wide data for managed and unmanaged modes. The address bus supports 10 [10:1] address bits for managed and unmanaged modes. Each device occupies 2048 bytes of Input/Output space.
10.1.4
Bus Master
The nomenclatures "Master" and "Slave" refer to the device that possesses the CPU Interface, or Control Bus, while the designations of "Primary" and "Secondary" refer to the device that possesses the Bus Arbiter. The primary or secondary device is determined during Power On/Reset, bootstrap options, while the master or slave device changes dynamically, and will be determined by the Arbiter. In managed mode, the systems' external CPU is the permanent master device. All other devices (e.g. the MDS213) are designated as slave devices only. In unmanaged mode, the arbiter (located within the primary device) selects one of the devices as the Master. Note: In unmanaged mode, the primary device may be the Master or the Slave. The master device is the bus master (controls the bus), while the other device is a slave device.
10.1.5
Input/Output Mapped Interface
The systems' external CPU accesses the switch devices' local memory using single-read/write or burst - read/write I/O cycles. Burst I/O operations with auto address incrementing uses a 32-byte write data buffer and a 32-byte cache read data buffer.
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Zarlink Semiconductor Inc.
MDS213
10.1.6 Interrupt Request
Data Sheet
The CPU Interface accepts an Interrupt Request (IRQ) from each device connected to the interface, and supports centralized interrupt arbitration and vector response. The interrupt output is an open-drain option with programmable polarity.
10.2
Control Bus Cycle Waveforms
Sample
Write Cycle Read Cycle Burst
P_CLK P_ADS# P_RDY# one-wait state P_A[10:1] P_D[31;0] P_BRDY# P_BLAST# Read Cycle = 8 clks
wait
wait Read
wait
Read Read Read Read
Figure 13 - Control Bus I/O
10.3
The CPU Interface in Unmanaged Mode
In unmanaged mode, the HISC processor of the Master device communicates with the slave device as a CPU function. Three registers and one flag are used to communicate between the HISC processor and the CPU Interface.
10.3.1
Arbiter
The arbiter of the XpressFlow MDS213 is an internal logic device used to determine which device will function as the master device. The connections between the master device, slave device, and the CPU are used for debugging purposes only. See Figure 14.
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
CPU
Only for Debug
P_GNTC MDS213 Primary
P_REQC MDS213 Secondary
Master state Machine
Bus Request Bus Grant Arbiter Chip select
P_REQ1 P_GNT1 P_CS
Master state Machine
Figure 14 - Block Diagram of the Arbiter Note: In unmanaged mode, the CPU is used only for debugging purposes and cannot be involved in switching decisions or management activities. During Power On/Reset, the bootstrap pin, BS_PSD, determines which device will be the primary and activates the arbiter of that device. At most, three devices, two MDS213 devices and one CPU, can operate on the CPU Interface at the same time. Each device may request access to the CPU Interface by sending a Request signal to the arbiter. The arbiter, then sends a Grant signal acknowledging which device has been chosen. An arbitrate scheduler, located within the arbiter, decides which device functions as the Master device. If the Master is the secondary device, the arbiter will send a Grant signal and a Chip Select (P_CS) signal to the device. If the Master is the primary device, the Grant signal is sent directly to the Master State Machine (MSM) by an internal signal. The scheduler then performs a round robin configuration and allows each device to be the Master device. Note: During Power On/Reset, the arbiter always selects the primary device to be master device.
10.4
CPU Interface in managed mode
The CPU Slave State Machine (SSM) accepts Address Strobe (P_ADS#), Chip Select (P_CS#), and Bus-Data Ready (P_RDY#) signals as ready state signals of a CPU cycle.
10.4.1
CPU Access
The 32-bit CPU bus interface supports both Big and Little Endian CPUs. The difference between Big and Little Endian is the byte swapping when CPU writes data to external memory. Table 15 summarizes the byte swapping operation and Figure 15 illustrates an example of bytes swapping. If using Little Endian If using Big Endian Bit[1] must be '0' for register of MWARS, MRARS, MWARB, MRARB Bit[1] must be '1' for register of MWARS, MRARS, MWARB, MRARB No byte swapping for CPU data write in or read out to/from MWDR, MRDR registers. Automatic Byte swapping for CPU data write in or read out to/from MWDR, MRDR registers.
Figure 15 - Little and Big Endian Byte Swapping Operation
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
31 CPU Bus Byte 0
24 23 Byte 1
16 15 Byte 2
87 Byte 3
0
31
Internal Data Bus Byte 3
24 23
Byte 2
16 15
Byte 1
87
Byte 0
0
Figure 16 - An example of byte swapping
11.0
11.1
The LED Interface
LED interface
The MDS213 LED interface supports the status per port in a serial stream that may be daisy-chained to connect two MDS213 chips. Daisy-chaining greatly reduces the pin count and number of board traces routed from the Physical Layer to the LEDs, thus simplifying system design and reducing overall system cost. For a large port configuration such as the 24+2 in the MDS213, a large number of LED signals is needed, which may induce noise and layout issues in the system. The LED information is transmitted in a frame-structured format with a synchronization pulse at the start of each frame.
MDS213 Master
MDS213 Slave
LE_CLKO LE_SYNCO LE_DO
LE_SYNCO LE_DO
LE_SYNCI LE_DI
LEDDECODER
LED-DISPLAY
Figure 17 - LED Interface Connections To provide the port status information from our MDS213 chips via a serial output channel, five additional pins are required. * * * LE_CLKO - at 12.5 MHz LE_SYNCI/O - a sync pulse -- defines the boundary between frames LE_DI/O - a continuous serial stream of data for all status LEDs which repeats once every frame time
A low cost external device (i.e. a 44-pin FPGA-like device) decodes the LED framed data and drives the LED array for display. This device may be customized for different system configurations.
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
The port status of the MDS213 is transmitted to an external decoder via a serial output channel. In the MDS213, we support cascading of this serial output channel between two devices. One MDS213 is configured as the master, this initiates the start of LED information frames, and serializes information bits. The MDS213 slave repeats the information sent from the master and appends its own information bits. To cascade these two devices, we will need to extend the number of LED pins from 3 to 5. Figure 17 shows two cascaded LED interfaces and the connections between the MDS213s, the LED decoder, and the LED display.
11.1.1
Function Description
The LED interface employs the following signals: Signal Name Master Device Slave Device LE_CLKO LE_SYNCI LE_DI LE_SYNCO LE_DO
Description LED Clock-Synchronous LED clock provided by the slave device to LED decoder at the system clock divided by 8 (~12.5Mhz). A synchronous pulse -- defines the boundary between frames. The length of each LED data frame is about 256 bits that shift out by LE_CLKO per bit. A continuous serial stream of data for all status LEDs which repeat once every frame time.
Table 7 - LED Signal Names and Descriptions
11.1.2
Port Status
In the MDS213, each port consists of 8 different LED status, represented by separate bits: 1. Flow Control 2. Transmitting Data 3. Receiving Data 4. Action (TxD or RxD) 5. Link UP/DOWN 6. Speed 7. Full Duplex/Half Duplex 8. Collision In addition to the 13 ports of the MDS213, three extra user-defined status sets may be sent through the LED serial channel for debugging or other applications, where each user-defined status set is also represented by 8 bits.
11.1.3
LED Interface Time Diagram
The Master needs to shift out (13+3)*8 status bits periodically. Thus, slave needs to shift out (13+3)*8 + (13+3)*8 status bits, which includes the status of the master device and itself. The status of each port will be sampled by the LED State Machine every 20.5 s, the time period of the frame. That is, each LED data frame length equals (256)X 80nsec. Each frame is divided into two subframes: a master and a slave sub-frame. Furthermore, each sub-frame is partitioned into 16 slots (13 MAC ports plus 3 user-defined sets) and each slot will carry 8 status bits. The following figure shows the signal from the slave chip to LED decoder.
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Zarlink Semiconductor Inc.
MDS213
One Frame Master dev sub-frame 16 slots 256x80nsec Slave dev sub-frame 16 slots
Data Sheet
Cycle #0 LED_CLKO LED_SYNCI/O
Cycle #1 Cycle #2
Cycle #3 Cycle #4
Cycle #5 Cycle #6 Cycle #7 Cycle #8
LED_DI/O
P0 bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
P1 bit 0
bit 1
1* one pulse for every 256 cycles
Figure 18 - Time Diagram of LED Interface
12.0
12.1 12.1.1
Data Forwarding Protocol and Data Flow
Data Forwarding Protocol Frame Reception
For normal frame reception, a 128-byte block of frame data is stored in the RxFIFO. This block may be shorter if an End of Frame (EOF) arrives. At that point, the RxDMA will request the use of the internal memory bus. When this memory request is granted, the RxDMA will move the block from the RxFIFO to the Frame Data Buffer (FDB). The MAC ports are partitioned into two groups, one for the Gbps Port and one for all 12 of the 100Mbps Ports. The service discipline is round robin for both the Gbps Port and 100/10Mbps group. After the entire frame is moved to the frame data buffer (FDB), a switch request will be sent to the Search Engine (Reference Search Engine Section)
12.1.2
Unicast Frame Forwarding
For forwarding of the unicast frame, the Search Engine first resolves the destination device and the destination port, and sends a switch response is sent back to the Frame Engine. The Frame Engine will obtain the type (unicast or multicast), the destination port, and the destination device from the search response. After processing the search response, the Frame Engine will notify the destination port that it has a frame to forward to the destination port's TxFIFO. For local forwarding (e.g. the destination port is in the local device), the Frame Engine will send the job to the Transmission Scheduling queue of the destination port. For remote forwarding (i.e. the destination port is in the remote device), the Frame Engine will create a data forwarding request command message (DATA_FWD_REQ), which is sent via the XPipe to the remote device. The remote Frame Engine, after receiving this DATA_FWD_REQ message, will place a job in the Transmission Scheduling queue of the destination port.The port will serve the next job from the Transmission Scheduling queue when the following two conditions are met: * * It is enough room for a 1.5Kbyte frame (a maximum-sized frame) within the TxFIFO. The end-of-frame (EOF) of the current frame has arrived at the TxFIFO.
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
There are four transmission-scheduling queues for each port, one for each of the four classes of priority. The port will send the jobs to the transmission scheduling queues according to a first in first out (FIFO) order. To start data transmission, the port obtains a job from the transmission scheduling queue and notifies the Transmit DMA (TxDMA) to move the data from the FDB to the MAC Transmit FIFO (TxFIFO) in 128-byte granules (for local forwarding). Otherwise, the device sends a DATA_REQ command message via the XPipe to the source device to request remote forwarding. The data forwarding engine module in the Frame Engine of the source device will then forward the frame in 128-byte granules via the XPipe.
12.1.3
Multicast Frame Forwarding
After the reception of the switching response, a job is sent to the Transmission Scheduling queues of the destination ports for local switching. However, for remote switching, one copy of the frame will be forwarded to the remote device in 128-byte granules via the XPipe. This copy of the frame will be sent to the frame data buffer. The Frame Engine, after the successful reception of this frame, will put jobs in the Transmission Scheduling queues of the destination ports of its device. When the TxFIFO is ready to receive the frame (same as the conditions stated in unicast frame forwarding section), the TxDMA will forward the frame from the FDB to the destination ports in granule form. The maximum size of a granule is 128 bytes.
12.2
Flow for Data Frame
The following subsections describe the flow of information during transfers of data frames, both unicast and multicast.
12.2.1
Unicast Data Frame to Local Device
In the simplest case, the data frame is destined for a port on the local device. The Frame Engine moves the received frame to the local FDB. The Search Engine forms a switch request with the frame header (includes source MAC and Destination MAC) and passes it to the Switch Engine to resolve the destination. The Switch Engine then provides a destination port address to the Frame Engine via a switch response message. Frame Engine transmits put a transmission job in transmission scheduling. After the port is ready to send the frame, then frame start to move the frame to TxFIFO. If the MAC address cannot be resolved by the Switch Engine, the HISC and/or the CPU are queried to resolve the address. For unknown destination MAC, the frame will flood the frame into the source VLAN domain.
12.2.2
Unicast Data Frame to Remote Device
In the case, the data frame is destined for a port on a remote device. First, the Frame Engine moves the received frame to the local FDB. A switch request with frame header (includes source MAC and Destination MAC) is passed to Switch Engine to resolve the destination. The Switch Engine then provides a destination port address to the Frame Engine. If the address resolution cannot be completed by the Switch Engine, the HISC and/or the CPU are queried. Once the address is resolved, the two Frame Engines performs the following interactive handshaking procedures via the XPipe: * * * Source Frame Engine sends a Data Forwarding Request message to Destination, where the destination Frame Engine puts a job in the associated transmission scheduling queue. When the destination port is ready to send the frame, the destination Frame Engine send a Data Request message to the source Frame Engine. After the source Frame Engine receives the Data Request Message, it start to move the frame in granule form, which is directly written in the destination TxFIFO.
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
Note that, at the remote device, the frame is written into the transmit FIFO of the remote destination port. The frame is not stored in the FDB of the remote device again, so that the latency can be reduce.
12.2.3
Multicast Data Frame
In this scenario, we assume that the multicast frame involve both local and remote ports. The received multicast frame is written to the local FDB by the Frame Engine. After resolving the destinations, the Switch Engine then provides local destination port addresses and remote port address to the Frame Engine. If the address resolution cannot be completed by the Switch Engine, the HISC and/or the CPU are queried. Frame Engine pushes the jobs to the corresponding transmission queues (per job per local port). When a local port is ready for this multicast frame, the Frame Engine moves the frame to the corresponding TxFIFO. There is a counter to track of the number of copies to be sent. The number is provided by Search Engine and the Frame Engine keeps track of this counter. When a frame is sent, the counter is decreased by one. The FDB will be released when the counter becomes zero. When the destination ports involve remote ports, the frame is transferred over the XPipe to the remote Frame Engine, which writes a single copy of it into the remote FDB. That is we use double store-and-forward for remote multicast. After receiving the whole frame, the remote Frame Engine utilizes the control information in the internal header, which indicates the associated destination ports in the remote device to push the jobs into the corresponding transmission queues. When a port is ready for this multicast frame, the Frame Engine moves the frame to the corresponding TxFIFO. Similarly, the Frame Engine also keeps track of the number of copy of frame to be sent and release the frame when the counter is reduced to be zero.
12.3
Flow for CPU Control Frame
In managed system, CPU may transmit or receive CPU control frames, e.g., Protocols, SNMP frames to/from a MAC port via a CPU unicast frame. On the other hand, a CPU may receive a multicast frame from a MAC port. Moreover, CPU can transmit a multicast frame to multiple ports. Use four scenarios to illustrate the forwarding flow.
12.3.1
CPU Transmitting Unicast CPU Frame
The CPU initiates Unicast control messages, by first writing the frame into the FDB, and then sending a message to the HISC. The HISC forwards a switch response to the Frame Engine, which transmits the frame to the destination MAC port. After receiving switch response, Frame Engine performs the same unicast forwarding as for unicast data frame. Refer previous subsection for unicast data frame mechanism.
12.3.2
CPU Transmitting Multicast CPU Frame
When the CPU sends a multicast control message to ports, the CPU first writes the frame to the local FDB. The CPU then sends a message to the HISC, which provides a switch response message to the local Frame Engine. After receiving switch response, Frame Engine performs the same multicast forwarding as for multicast data frame. Refer previous subsection for multicast data frame mechanism.
12.3.3
CPU Receiving Unicast Frame
The receiving CPU frame is moved to FDB and the Frame Engine forwards a switch request including the frame header to Search Engine. After Search Engine decodes the header and determines to forward it to HISC to process. HISC informs the CPU via a mail, which indicates the handle of FDB. CPU then obtains the frame through the MDS213. After read the frame from FDB, CPU will inform HISC to release the FDB. Finally, HISC passes the release command to Frame Engine to release the FDB accommodated CPU frame.
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Zarlink Semiconductor Inc.
MDS213
12.3.4 CPU Receiving Multicast frame
Data Sheet
The MDS213 is capable of receiving a multicast packet for a combination of local ports, remote ports, and also the CPU. In this case, the received frame includes multicast destination ports on a remote device, and also the CPU. The Frame Engine moves the multicast frame to FDB and then form a switch request including the frame header to Search Engine. Since the frame involves CPU, the Search Engine passes the request to HISC for further process. HISC informs CPU via a mail, which indicates the handle of FDB. In parallel, the Search Engine sends back a switch response and ask Frame Engine to forward the frame to destinations ports. Frame Engine will perform the same multicast forwarding as mentioned above. CPU read the frame from FDB via MDS213. After read the frame from FDB, CPU will inform HISC to release the FDB. Finally, HISC passes the release command to Frame Engine to release the FDB accommodated CPU frame. Note that the Frame Engine won't release FDB until it receives the release signal from HISC and also the counter is reduced to zero. That means all the ports and CPU have read out the frame.
13.0
13.1
Port Mirroring
Features
The received or transmitted data of any 10/100 port in any MDS213 chip, connected by Port Mirror signal pins, PM_DO and PM_DI, can be chosen to be mirrored to the "Mirror Port." The mirror port can be the first port in a MDS213 with RMII or a dedicated mirror port with MII, driven by the pin, PM_DO[0:1]. Once the first RMII port of a chip is selected to be the mirror port, it cannot be used to serve as a data port. The configuration of port mirroring is shown in the following diagram, based on the current evaluation board design.
PM_DO[1:0] PM_DENO MDS213 Chip 0
PM_DI[1:0] PM_DENI MDS213 Chip 1
PM_DO[1:0] PM_DENO
4 FE RMII Port 0123 Mirror port
4 FE RMII 4567
4 FE RMII 8 9 10 11
1 GMII 12
4 FE 1 4 FE GMII RMII RMII 13 14 15 16 17 18 19 20 21 22 23 24 25 Mirror port
4 FE RMII
MII PHY Mirror Port
Port 0 can be RMII mirror port and mirror port 1-11. Port 13 can be a RMII mirror port and mirror port 0-11, 14-24. Dedicated MII mirror port can mirror port 0-11, 13-24.
Figure 19 - Configuration of Mirror Port for MDS213
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Zarlink Semiconductor Inc.
MDS213
13.2 Physical Pins
Data Sheet
There are 6 related pins to Port Mirroring functions: * PM_DI [1:0] Port Mirroring Input Data Bit [1:0]
Receive the mirrored data signal from the remote MDS213. * PM_DENI Port Mirroring Data Enable signal for PM_DI Input
Provide Data Enable signal for PM_DI signals * PM_DO[1:0] Port Mirroring Output Data Bit [1:0]
Transmit the mirrored data signal to remote MDS213. * PM_DENO Port Mirroring Data Enable Output.
Provide Data Enable signal for PM_DO signals Refer to Figure 20 for connecting above pins.
13.2.1
Setting Register For Port Mirroring
The APMR register controls the mirrored port, the designated mirroring port. The definition of the register is shown as follows:
13.2.1.1
APMR- Port Mirroring Register
31 15 14 13 12 MP Rx/ L/R 0 Tx 11 Mirror Port 0
Bit [11:0]Mirr_Port10/100 port is chosen to be mirrored, (port bit map) Bit [12] Local/RemoteIndicate the mirrored port from local or remote device. 0=local 1=remote (Note: Not support 1G port Mirroring.) Note that at most only one of bit in Bit[11:0] can be set to 1. Bit [13] Rx/TxWhether mirror receiving data or transmitting data 0= Transmission Mirroring, 1=Receiving Mirroring Bit [14] MP0Mirror to Port 0 (Default=0) MP0=1 Mirror to port 0 MP0=0 Mirror not go to port 0. i.e., to PM_DO pins. Bit [31:15]Reserve We use examples to illustrate how to set the APMR register. The following examples are based on the configuration of Figure 20.
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Zarlink Semiconductor Inc.
MDS213
Example 1: Mirroring port 1 to port 0 and Mirror transmission direction. For Chip 0 Set APMR[11:0]=0x002; mirrored port= 1 Set APMR[12]=0 ; local mirrored port Set APMR[13]=0; Transmission mirroring Set APMR[14]=1; Port 0 is the mirroring port For Chip 1: Don't Care Example 2: Mirroring port 1 to port 13 and Mirror receiving direction. For Chip 0 Set APMR[11:0]= 0x002; mirrored port= 1 Set APMR[12]=0 ; local mirrored port Set APMR[13]=1; receiving mirroring Set APMR[14]=0; Port 0 is not the mirroring port For Chip 1: Set APMR[11:0]=0x000 Set APMR[12]=1 ; remote mirrored port Set APMR[13]=Don't careBit[13] has meaning only in the chip of mirrored port Set APMR[14]=1; Port 13 is the mirroring port Example 3: Mirroring port 1 to MII Mirroring port Mirror receiving direction. For Chip 0 Set APMR[11:0]= 0x002; mirrored port= 1 Set APMR[12]=0 ; local mirrored port Set APMR[13]=1; receiving mirroring Set APMR[14]=0; Port 0 is not the mirroring port For Chip 1: Set APMR[11:0]= 0x000 Set APMR[12]=1 remote mirrored port Set APMR[13]= Don't careBit[13] has meaning only in the chip of mirrored port Set APMR[14]=0Port 13 is not the mirroring port
Data Sheet
Note that CPU needs to find out the speed of the mirrored port and configures the mirroring port to the same speed.
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Zarlink Semiconductor Inc.
MDS213
14.0
14.1
Data Sheet
Virtual Local Area Networks (VLAN)
Introduction
A Virtual LAN (VLAN) is a logical, independent workgroup within a network. The members in this workgroup communicate as if they are sharing the same physical LAN segment. VLANs are not limited by the hardware constraints that physically connect traditional LAN segments to a network. As a result, VLANs can define a network into multiple logical configurations.
14.2
VLAN Implementation
The MDS213 based VLAN implementation allows up to 256 VLANs in one switch. By using explicit or implicit VLAN tagging and the GARP/GVRP protocol (defined in IEEE 802.1p and 802.1Q), VLANs may span across multiple switches. A MAC address can belong to multiple VLANs, and a switch port may be associated with multiple VLANs.
14.2.1
Static Definitions of VLAN Membership
The MDS213 defines VLAN membership based on ports. Port based VLANs are organized by physical port numbers. For example, switch ports 1, 2, 4, and 6 can be one VLAN, while ports 3, 5, 7, and 8 can be another VLAN. Broadcasts from servers within each group would only go to the members of its own VLAN. This ensures that broadcast storms cannot cause a network meltdown due to traffic volume.
14.2.2
Dynamic Learning of VLAN Membership
While port based VLAN only defines static binding between a VLAN and its port members, the MDS213's forwarding decision needs to be based on the following: * * A destination MAC address and its associated port ID for a unicast frame, or The associated VLAN of a source MAC address, if the destination MAC address is unknown or it is a multicast/broadcast frame. To make valid forwarding and flooding decisions, the MDS213 learns the relationship of the MAC address to its associated port number and VLAN ID and builds up the internal Switching Database at run-time for further use.
14.2.3
Dynamic Learning of Remote VLAN
In addition to adding and deleting VLAN member ports through network management tools statically, a MDS213 based switch can also support GVRP (GARP VLAN Registration Protocol). GVRP allows for dynamic registration of VLAN port members within a switch and across multiple switches. In addition to supporting the dynamic update of registration entries in a switch, GVRP is also used to communicate VLAN registration information to other VLANaware switches, so that a VLAN member can be covered by a wide range of switches in a network. GVRP allows both VLAN-aware workstations and switches to issue and revoke VLAN memberships. VLAN-aware switches register and propagate VLAN membership to all ports belonging to the active topology of the VLAN.
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Zarlink Semiconductor Inc.
MDS213
14.2.4 MDS213 Data Structures For VLAN Implementation
63 0
Data Sheet
FDB Frame Data Buffers
FDB block must start from 0
Transmission queues
Programmable Size
External RAM CPU/HISC Mailing List VLAN ID Table (4k entry, 8B/entry) VLAN MAC Table (2k entry, 256/128/64 bit) MAX 1/2MB, 1MB or 2MB Byte Byte Byte ByteByte ByteByte Byte 7 6 5 4 3 2 1 0 Programmable Size
32KB
64, 32 or 16KB (up to the number of supported VLAN)
Figure 20 - Data Structure Diagram
14.2.4.1
VLAN ID Table
The VLAN ID Table is used by Search Engine for unicast frames. The base address of this table is specified by VIDB subfield in BIT[5:0] of VTBP register. The contents of this table are set up by the MDS213's microcode through the command of CPU software at the time of VLAN creation and deletion. The VLAN ID Table covers the entire 4K VLAN ID space, and is used by the Search Engine to map the VLAN ID into an internal VLAN Index. It also includes port membership and port tagging information for each VLAN. Each VLAN ID entry is 8 bytes long, and the total size of the VLAN ID Table is 32KB. The VLAN ID table must be located at the 32K boundary.
Byte 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1098765432109876543210 0 Index[3: C V P12P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 T S 0] P28 P17P16 Index[7: 4 4]
Figure 21 - VLAN ID Table Bit[1:0] P0VLAN Status for Port 0 Bit [0]SThis port is a member of this VLAN Bit [1]TTagout
Bit[3:2] P1 VLAN status for Port 1 ....
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Zarlink Semiconductor Inc.
MDS213
Bit [26]VVLAN is Valid Bit [27]CCPU is a member of this VLAN Bit [31:28]1st byte: VLAN Index [3:0], 2nd byte: VLAN Index [7:4]
Data Sheet
Note: P0 to P12 are used to identify the ports on the first chip, while P16 to P28 are used to identify the ports on the second chip.
14.2.4.2
VLAN MAC Table
The size of this table is defined by VLMS subfield in BIT[8:7] of VTBP register. The base address of this table is specified by VMACB subfield in BIT[15:9] of VTBP register. The VLAN MAC Table contains all associated VLANs for each MAC Address learned by MDS213, and is used by the software to keep track of every MAC and its associated VLANs. The contents of this table are set up by the Search Engine at the reception of incoming frames, if the Search Engine is not fully occupied. When the Search Engine is too busy handling frame forwarding decisions, microcode in the HISC engine will be assigned the setup new MAC to VLAN associations. Rows in this table can be cleared up by microcode through a CPU software command during VLAN deletion or port link down. A row in this table will be cleared and a new bit set up by the MDS213's microcode, when the port change of a MAC address is detected. There is a total of 2K entries in this table, one entry per MAC. Each entry may consist of 256, 128 or 64 bits, one bit per VLAN. The total size of the VLAN Table may be 64, 32 or 16KB. This table must be located at the boundary of its own table size.
MAC handle 0 1 2 3 . . . . . . . .. . . 2K
0 1 2 3 .........................
100
256
VLAN ID
Figure 22 - VLAN MAC Table This table can be accessed by CPU software through CPUIRCMD and CPUIRDAT registers.
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Zarlink Semiconductor Inc.
MDS213
14.2.4.3 VLAN Port Mapping Table (VMAP)
Data Sheet
The VLAN Port Mapping Table (VMAP) is an internal table within the MDS213. It contains 256 entries, one for each VLAN, identified by an internal VLAN Index. The contents of this table are set up and maintained by CPU software during VLAN creation, deletion and VLAN port membership modification. VMAP is used by Frame Engine to forward multicast or destination unknown unicast frames to multiple ports simultaneously.
31
27 26 25 RE VLAN Port Enable [12:0]
13 12 TAG Enable [12:0]
0
Bit [12:0]VLAN Tag Enable [12:0]One bit for each Ethernet MAC Port 0 = disable, 1 = enable Bit [25:13]VLAN Port Enable [12:0]One bit for each Ethernet MAC Port, identifying the ports associated with each VLAN. 0 = disable, 1 = enable Bit [26]RE Remote Ports Enable: Indicate some members in the remote device.0=disable, 1=enable Bit [31:27]Reserve
14.2.4.4
Port VLAN ID (PVID) Register
This register defines the Port VLAN ID (PVID) and priority for each port. PVID needs to be set up by CPU software, and is used by MDS213 to decide the port's VLAN ID and priority if the incoming packet is VLAN untagged.
31
24 23
16 15 Priority
13 12
11
87 Port VLAN ID
0
Bit [11:0]:Port VLAN ID (PVID), Bit [12]:Reserved Bit [15:13]: Priority Bit [31:16]:Reserved
15.0
15.1
IP Multicast
Introduction
IP Multicast permits an IP host (source) to transmit a single IP packet to multiple IP hosts (receivers). IP Multicasting allows a source to send only one copy and the network ensures delivery to each member of the specified multicast group. Network bandwidth is allocated more efficiently, as multiple copies of the same frame are not transmitted between common ports. The packet destined to an IP multicast group address determines the set of recipients. Hosts may choose to be members of a number of multicasts, and hence select the multicast packets they wish to receive. They may subscribe or unsubscribe to these multicast groups dynamically, using the Internet Group Management Protocol (IGMP) that support automatic multicast group membership. IGMP is configured to create, update, and/or remove
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
dynamic multicast group entries between switches and multicast clients and servers. RFC 1112 specifies the protocols and behaviour for IP Multicasting. The MDS213 supports up to 255 IP Multicast Groups and treats them as extensions of the VLAN operation. No additional hardware is needed, since the IGMP operates on the hardware already provided for VLAN functionality. IGMP packets are identified by the Search Engine and are passed to the external CPU for processing, when the destination MAC address is 01-00-5E-xx-xx-xx, Protocol field value equals 2 and the destination IP address is 224.0.0.x. The external CPU then instructs the HISC to setup IP Multicast entries for the MAC Addresses in the Switch Database Memory, the VLAN Table, and the MCT-VLAN Table. The HISC builds and maintains an MCTVLAN and a VLAN Table for IP Multicast Groups in the Frame Buffer Memory. When an IP Multicast packet is received, it is identified by a specific class of Multicast Destination MAC addresses, where the high-order bits indicate use of IGMP, and the low-order bits indicate the specific IGMP Group Identifier. The MDS213 searches the MCT VLAN Association Table for destination MAC addresses, using the IGMP or the IGMP Group Identifier stored in the MCT, to obtain port membership for the IP Multicast Group. The Search Engine forwards the packet to each port associated with the IP Multicast Group. Where no address is found, the HISC firmware updates the MCT-VLAN to include this address. The Multicast Buffer Control Register (MBCR) allows the configuration of multicast frames to be forwarded, the number of buffers reserved for receiving remote multicast frames, the number of multicast frames allowed, and the multicast forwarding threshold.
15.2
IGMP and IP Multicast Filtering
IP multicast filtering optimizes switched network performance by limiting multicast packets to only be forwarded to ports containing multicast group membership instead of flooding all ports in a subnet (VLAN). The Internet Group Management Protocol (IGMP) runs between hosts and their immediate neighboring multicast routers. The mechanism of the protocol allows a host to inform its local router that it wishes to receive transmissions addressed to a specific multicast group. Routers, also, periodically query the LAN to determine if known group members are still active. Based on the group membership information, learned from the IGMP, a router is able to determine which (if any) multicast traffic needs to be forwarded to each of its "leaf" sub-network. Multicast routers use this information, in conjunction with a multicast routing protocol, to support IP multicasting across the Internet. The MDS213 based switch supports IP Multicast Filtering by passively snooping on the IGMP Query. The IGMP Report packets are transferred between IP Multicast Routers and IP Multicast host groups to learn the IP Multicast group members within each VLAN actively sending out IGMP Query messages soliciting IP Multicast group members. They thus learn the location of multicast routers and member hosts in multicast groups within each VLAN. Since IGMP is not concerned with the delivery of IP multicast packets across sub-networks, an external IP multicast router will be needed if the IP multicast packets have to be routed across different IP sub-networks.
15.3
Implementation in MDS213
The MDS213 supports up to 255 IP Multicast Groups and treats them as an extension of the VLAN operation. No additional hardware is needed, since IP Multicast Switching/Filtering already operates in hardware provided for VLAN functionality. IGMP packets are identified by the Search Engine and are passed to the external CPU for processing, when the destination MAC address is 01-00-5E-xx-xx-xx, Protocol field value equals 2 and the destination IP address is 224.0.0.x. The external CPU then instructs the HISC to setup an MCT entry for this IP Multicast Address in the Switch Database Memory. If this is a new IP Multicast group, it sets up an entry in the VLAN Port Mapping Table by itself.
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
Whenever an IP Multicast data packet (destination MAC = 01-00-5e-xx-xx-xx, and destination IP address is within the range of 224.0.1.0 and 239.255.255.255) is received, the Search Engine will use the MCT table to look up the IP Multicast address of the incoming packet. Frame Engine then will use the result from the search (VLAN Index) to forward this IP Multicast packet to its member ports according to the VLAN Port Mapping Table.
15.3.1
MCT Table
The MCT table is an internal table within the MDS213 chip that has a total of 2K entries. The CPU setups and read the table one entry at a time through microcode in the HISC. There are two types of overlapped MCT entries, one used for layer-2 MAC address based unicast switching, and the other for IP Multicasting.
15.3.1.1
MCT Structure For Unicast Frame
The MCT table is used by the Search Engine to forward unicast frames. By looking up a destination MAC address from this table, the associated port number is found and used for packet forwarding decisions. The content of the table is set up by the Search Engine at the reception of an incoming frame, if the Search Engine is not fully occupied. When the Search Engine is too busy handling frame forwarding decisions, microcode in the HISC engine will be assigned to do the learning job by setting up new MAC to Port associations. An entry in this table can be setup by microcode in HISC through a CPU software command for static layer-2 packet filtering based on either the source or destination address. An entry can be cleared by microcode in the HISC through a CPU software command, during VLAN deletion, port link down, or when it is aged out. It will also be cleared and a new one set up when a port change of a MAC address is detected.
Byte 3 3 2 2 2 2 2 2 2 109876543 0 MAC3 S 4 S P 8 12
22211111111119876543210 2109876543210 T MAC2 MAC1 MAC0 D Port number MAC5 MAC4 Next Handle
T:
Time stamp, used for aging. Set to 1 after MAC is found, and cleared to 0 when aged.
MAC[5:0]:MAC Address S: D: Source MAC address filtering Destination MAC address filtering
SP: Transmit Speed. 1- Gbps, 0-100Mbps Next Handle: Pointer to the next entry in a hashed link list.
15.3.2
MCT structure for IP Multicast Packet
An IP Multicast entry in the MCT table can be setup or torn down by microcode in HISC through a CPU software command for IP Multicasting. Whenever an IP multicast data packet is received, the Search Engine will use this table to look up the IP Multicast address and VLAN ID of the incoming packet. If the IP Multicast address is found, an internal VLAN Index from the MCT entry will be used by the Search Engine and Frame Engine to forward the IP Multicast packet to the specific IP Multicast group members in a VLAN. If not, the packet will be forwarded to the VLAN it belongs to.
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Zarlink Semiconductor Inc.
MDS213
Byte 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1098765432109876543210 0 VLAN ID IP1 IP0 4 C VLAN Index IP3 IP2 P U 8 Next Handle 12
Data Sheet
VLAN ID:The VLAN ID this IP Multicast group is located in. IP[3:0]:IP Multicast Address VLAN Index:Internal VLAN Index used to identify this IP Multicast group CPU:1: Switch CPU is part of this IP Multicast group Next Handle: Pointer to the next entry in a hashed link list.
16.0
Quality of Service (QOS)
Quality of Service (QoS) provides the capability to reserve bandwidth throughout the network. This is particularly useful for sending voice or video over the switched network. In a switched Ethernet environment, this is only possible with Resource Reservation Protocol (RSVP), a Layer 3 protocol. In a Layer 2 switch, QoS, referred as Class of Service (CoS) by the IEEE 802.1Q standard, provides the capability to prioritize certain tasks on the network. This is done at the application level, where applications can set the priority when the frame is created. The MDS213 classifying Ethernet frames according to their IEEE 802.1p/Q VLAN priorities. There are three bits in the VLAN ID reserved to designate the priority of a packet. Each port stores its transmission jobs into four transmission scheduling queues, one for each priority. Before transmitting, a port selects a queue from which a transmission job is read. The transmission job points to a frame stored in memory that is fetched and transmitted. The four queues, representing four classes of traffic, are selected using a weighted round robin (WRR) strategy. The relative service rates among these queues are programmable such that bandwidth can be allocated according to classes. This ensures that critical applications get a fair share of bandwidth, even when the network is overloaded. The Search Engine recognizes the IEEE 802.1p priority tag and classifies each incoming frame into four internal priority classes: P0, P1, P2 and P3, in decreasing priority. Since the IEEE 802.1p/Q allows up to eight priorities, a programmable mapping allows the user to map the 802.1p priority to the internal priority tag via register AVTC.
16.1
Weighted Round Robin Transmission Strategy
Frames of four different priorities are transmitted according to a weighed round robin (WRR) strategy. The WRR is a modified form of the fair round-robin strategy, in which the server visits the queues in turn. In a fair round-robin strategy, the server treats all queues equally and visits them with identical frequency. In a WRR, the queues are weighted, i.e., one queue may be visited more frequently than another. These weighs are programmable via register AXSC, in which the service rate ratio between two adjacent classes of traffic is set. In register AXSC, setting QSW0=2, QSW1=QSW2=1 gives the service ratio 8:2:1:1, which is a good start for most LAN switches. This ratio allocates 67% = 8/12 of bandwidth to P0, 16% = 2/12 of bandwidth to P1, and P2 and P3 each receives 8.3% = 1/12 of bandwidth, assuming all frames have identical frame length.
16.2
Buffer Management Functions
The MDS213 stores frame data in frame buffers. The number of frame buffers in a system is the maximum number of frames a device can store. When all frame buffers are used, incoming frames cannot enter the memory and are discarded. Without buffer management, a congested port causes a backlog of frames that eventually occupy all
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
frame buffers. The MDS213 features buffer management functions that prevent a single type of traffic from depleting all frame buffers. The buffer manager limits the number of frames each destination port can store, thereby preventing congested ports from occupying all the buffers and blocking incoming frames. The buffer manager examines the destination port of every frame stored, and increments a counter associated with this destination port. These buffer counters keep track of the number of buffers occupied by frames destined to each port. If the counter reaches a threshold, incoming frames destined for the associated port will be dropped. This threshold is programmable via register BCT and BCHL. Register BCT allows the user to program two thresholds, one high and one low. The user specifies a threshold, high or low, for each port in register BCHL. The buffer manager also prevents multicast frames from occupying all frame buffers. A programmable threshold, register MBCR, limits the number of multicast frames stored in memory. In another word, buffers are reserved for unicast frames.A multicast forwarding job points to a multicast frame in memory fetched and forwarded by the Frame Engine across the XPipe to the remote device. The Frame Engine can only forward a handful of multicast frames simultaneously across the XPipe. Excess multicast forwarding jobs are stored in an internal FIFO, called the MC-Forwarding-FIFO. If the MC-Forwarding-FIFO is full, incoming multicast frames can no longer be forwarded to the remote device. The MDS213 has a programmable option to recognize IP multicast (IPMC) frames. By default, IPMC frames are treated equally with Layer 2 multicast frames. This option gives IPMC privilege, in terms of buffer allocation, over regular Layer 2 multicast frames. In a broadcast storm, Layer 2 multicast frames are discarded before IPMC frames. The system has the flexibility to recognized a programmable IPMC MAC address signature, set by registers IPMCAS0, IPMCAS1, IPMCMSK0 and IPCMMSK1. If a programmable option, DCR2, bit 26, is turned on, the system reserves space in the MC-Forwarding-FIFO for IPMC frames. This ensures that Layer 2 multicast frames do not block IPMC frames.
17.0
Port Trunking
Port trunking groups a set of 8 MDS213 10/100Mbps physical ports into one logical link; however, all ports in the trunk group must be within the same access device, and each port can only belong to one trunk group. All ports in the Trunk group must belong to the same VLAN and share the same MAC Address. Each system can support up to 4 groups. Gigabit ports cannot be trunked. Load distribution for unicast and multicast traffic is done based on a hash key, a hash function of the Source Address and the Destination Address.
17.1
Unicast Packet Forwarding
A trunked port will need to have its ECR1 MAC Port Configuration Register set by CPU software to contain its associated Trunk Group ID. Later on, when a new source MAC Address is learned through that port, the Trunk Group ID will be recorded in the MCT entry by either the Search Engine or the microcode in the HISC. The Trunk Group ID will be used for forwarding decision when the destination MCT entry of a received packet is found by the Search Engine, if the status field indicates that the address found is on a Trunk Group. The Trunk Group ID is used by the Search Engine, along with the "hash key" (3 bits result of a hash operation between source address and destination MAC address), to access a Trunk Port Mapping Table entry in the internal RAM. Each entry in this table contains the device and port IDs for the physical port used to transmit this packet. Software needs to set these entries, using TPMXR and TPMTD registers, to distribute the traffic load across the ports in the Trunk Group. If the source MAC Address of an incoming packet is on a Trunk Group (based on the MCT information), the receiving port's TGID will be compared against the Trunk Group ID in the source MCT to decide whether the source MAC address has moved to another Trunk Group or not.
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Zarlink Semiconductor Inc.
MDS213
Data Sheet
TG provided by Search Eng
Dev ID (1 bit)
Port ID (4 bit)
TG Hash Key (2 bits) (3 bits) Hash Keys
. . . . . .
Port Mapping Table for MDS213
32 entries
Figure 23 - Port Mapping Table In Figure 23, the Trunk Port Mapping Table is 32 entries deep (4 groups * 8 hash entries), and each entry is 5 bits wide (1-bit device ID, 4-bit port ID), as show in the following format.
17.2
Multicast Packet Forwarding
For multicast packet forwarding, the destination device must determine the proper set of ports to transmit the packet based on the VLAN Index and Hash Key, generated by the source Search Engine. Two functions are needed to distribute multicast packets to the appropriate destination ports in a Trunk Group. 1. Selecting a Forwarding Port per Trunk Group: Only one port per Trunk Group will be used to forward multicast packets. This can be done with a VLAN INDEX Table and a Forwarding Port MASK Table set up by CPU. 2. Blocking Multicast Packet Back to the Source Trunk: For multicast forwarding that includes ports in Trunk Groups in the same device as source port, all ports in the same Trunk Group at the receiving port must be excluded. Otherwise, this multicast packet will be looped back to the same source Trunk Group. This is achieved through a Trunk Group ID Register that contains 36 bits (36=12x3).
17.2.1
Select One Forwarding Port per Trunk Group
To forward multicast frames, the Frame Engine retrieves the VLAN member ports from one of the 256 entries in the VLAN Port Mapping Table (VMAP) as described in the VLAN section. By using the Hash Key and the Forwarding Port Mask table, the Frame Engine can obtain the corresponding FP Mask. The final forwarding ports can then be determined by the logical AND of the FP Mask and the VLAN Member Port bit map. The Forwarding Port- Mask Table must be set by the CPU to THKM[0:7] registers beforehand. The format of this table and the method of setting it up are shown below.
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Zarlink Semiconductor Inc.
MDS213
Forwarding Port MASK Registers (12 bits)
Data Sheet
3-bit Hash Key 8 entries in table
CPU sets up this table as follows: 1. Set up one entry of these registers at a time until table is exhausted. 2. Set all bits not in any Trunk Group to 1. 3. Set all bits in the Trunk Groups to 0. 4. Pick one forwarding port per Trunk Group and turn the corresponding bit to 1. (Each Hash Key may have different forwarding port, the rule to pick forwarding port is up to CPU)
VLAN Member Port AND
FP Mask
Forwarding Ports
Figure 24 - Forwarding Port Mask Table Two restrictions exist in setting up tables: 1. When setting up the VLAN Port Mapping Table, all the ports in the Trunk Group must be set to 1, if the VLAN has ports in any Trunk Group.
2. When setting up the Forwarding Port Mask Table, the CPU software picks only one forwarding port per Trunk Group.
17.2.2
Blocking Multicast Packets Back to the Source Trunk
For local multicast packets, the Frame Engine needs to block the multicast packets from being sent to the same Trunk Group as the receiving (source) port. To do it, the Search Engine utilizes the Trunk Group ID (TGID) in ECR1 Register. The Frame Engine compares the TGID of the source and forwarding ports. If the two TGIDs are the same, the Frame Engine blocks the forwarding port for this multicast packet. The Switch Engine provides the TGID of the source port. Example The following is an example demonstrating this port trunking scheme for multicast packet forwarding: 4 Trunk Group in a switch: Group 0: port 0,1,2 in device 0 Group 1: port 4, 5,6 in device 0 Group 2: port 1, 2,3 in device 1 Group 3: port 4, 5,6 in device 1 A multicast packet with VLAN INDEX=5 is received at port 0 of device 0. The membership of this VLAN: Device 0: port 0,1,2, 4,5, 6, 7 Device 1: port 1,2, 3, 4,5,6, 8
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Zarlink Semiconductor Inc.
MDS213
Hash Key = 3 Forwarding Port for each group with Hash Key=3, Port 2 for Group 0 Port 4 for Group 1 Port 3 for Group 2 Port 6 for Group 3
Device 0 Local 0 1 2 3 4 5 6 7 ...........12 0011100111111 1110111100000 Device 1 Remote 0 1 2 3 4 5 6 7 ...........12 1001001111111 0111111010000 A N D
Data Sheet
A N D
Forwarding Port Mask for Key=3 VLAN Member for INDEX=5
Forwarding Ports Turn this port off since port 2 has 0000100100000 the same TGID of Multicast packet received at port 0 of device 0 source port 0 VLAN IDX=5, Hash Key=3 0010100100000
0001001010000
Figure 25 - Multicast Packet Forwarding Example
17.3
MAC Address Assignment
In MDS213, there are three ways to assign the MAC address to each port. All the ports in the same device share the 44 MSBs, MAC[47:4], which are shown in ADAR0 and ADAR1 registers, while the 4 LSBs, MAC[3:0] are specified in ADAOR0 and ADAOR1 registers for port 0-port 7 and port 8-port 12, respectively. The method to assign the 4 LSBs MAC[3:0] can be assigned as follows: * * * If the switch does not support Port Trunking, MAC[3:0]= port number If the switch supports multiple MAC addresses and Port Trunking, the ports in the same Trunk Group share the same MAC[3:0]. The value of MAC[3:0] is assigned by the Trunk Group (TG) Table. If the switch supports only a single MAC address, all the 4 LSBs of MAC will be set the same value in ADAOR0 and ADAOR1 register.
18.0
18.1
Register Definitions
Register MAP
All registers are grouped into sets:. * * * * * * * * Device Configuration Buffer Memory Interface Frame Control Buffer Queue Management Switching Control Link List Management Access Control Functions MAC Port Control
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Access Control: W/R = These register bits may be read from and written to by software W/-- = These register bits may be written to by software, but not read. Write Only (--/R) = These register bits may be read but not written to by software. Read Only Latched and held bits Clear bits Permanently set bits All registers are 32-bit wide. They are classified in the following tables: Tag Description Address
Data Sheet
W/R
1. Device Configuration Registers (DCR) GCR DCR0 DCR1 DCR2 DCR3 MEMP ISR ISRM IMSK IAR MWARS MRARS MWARB MRARB MWDR MRDR VTBP MBCR RAMA Reserve Reserve Global Control Register Device Status Register Signature & Revision & ID Register Device Configuration Register Interface Status Register Memory Packed Register Interrupt Status Register - Unmasked Interrupt Status Register - Masked Interrupt Mask Register Interrupt Acknowledgement Register Memory Write Addr. Reg. - Single Cycle Memory Read Addr. Reg. - Single Cycle Memory Burst Write Address Register Memory Burst Read Address Register Memory Write Data Register Memory Read Data Registers VLAN ID & MAC member Table Base Pointer Mulitcast Buffer Control Register RAM block access Register Must Set to "0x0001 0008" Must Set to "0x0001 0000" Table 8 - MDS212 Register Map 7C0 7C0 7C4 7C8 7CC 7DC 7E0 7E4 7E8 7EC 780 784 788 78C 790 794 798 79C 7A0 7B8 7BC W/---/R W/R W/R --/R W/R --/R --/R W/R W/-W/-W/-W/-W/-W/---/R W/R W/R W/R W/R W/R
2. Interrupt Controls
3. Buffer Memory Interface
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Tag 4. Frame Control Buffers Management FCBSL FCBST BCT BCHL CINQ COTQ HPCR HMCL0 HMCL1 HPRC MCS0R MCS1R FCR MCAT TPMXR TPMTD PTR MTCR LKS AMBX AFML AVTC AXSC ATTL AMIIC AMIIS AFCRIA AFCRID0 AFCRID1 FCB Stack Size Limit Frame Ctrl Buffer Stack - Buffer Low Threshold Buffer Counter Threshold Buffer Counter Hi-Low Selection CPU Input Queue CPU Output Queue HISC Processor Control Register HISC Micro-Code Loading Port-Low HISC Micro-Code Loading Port-High HISC Priority Control Register Micro Sequence 0 Register Micro Sequence 1 Register Flooding Control Register MCT Aging Timer Trunk Port Mapping Table Index Register Trunk Port Mapping Table Data Register Pacing Time Regulation MCT Threshold & Counter Register Link List Status Register Mail Box Access Port Free Mail Box List Access Port VLAN Type Code Transmission Scheduling Control Register Transmission Timing & Threshold Control Register MII Command Register MII Status Register Flow Control Ram Input Address Flow Control Ram Input Data Flow Control Ram Input Data Table 8 - MDS212 Register Map (continued) 740 744 74C 750 708 70C 6C0 6C4 6C8 6D0 6D4 6D8 6DC 6E0 6E4 6E8 6EC 6F0 680 684 688 648 64C 650 654 658 65C 660 664 Description Address
Data Sheet
W/R
W/R W/R W/R W/R W/--/R W/R W/R W/R W/R W/R W/R W/R W/R W/-W/R W/R W/R W/R W/R W/R W/R W/R W/R W/---/R W/-W/R W/R
5. Queue Management
6. Switching Control
7. Link List Management
8. Access Control Function Group 1 (Chip Level controls)
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Tag AFCR AMAR0 AMAR1 AMCT ADAR0 ADAR1 ADAOR0 ADAOR1 ACKTM AFCOFT10 AFCOFT100 AFCOFT1000 AFCHT10 AFCHT100 AFCHT1000 APMR PFR THKM0 THKM1 THKM2 THKM3 THKM4 THKM5 THKM6 THKM7 IPMCAS0 IPMCAS1 IPMCMSK0 IPMCMSK1 CFCBHDL CPUIRCMD CPUIRDAT0 Flow Control Register Multicast Addr. For MAC Control Frames Byte [3,2,1,0] Multicast Addr. For MAC Control Frames Byte [5,4] MAC Control Frame Type Code Register Base MAC Address Register - Byte [3,2,1,0] Base MAC Address Register - Byte [5,4] MAC Offset Address Register Port [7:0] MAC Offset Address Register Port [12:8] Timer for SOF Check Flow Control Off Time for 10Mbps port Flow Control Off Time for 100Mbps port Flow Control Off Time for Giga port Flow Control Holding Time for 10 port Flow Control Holding Time for 100 port Flor Control Holding Time for Giga port Port Mirroring Register Protocol filtering Register Trunking Forward Port Mask 0 (hash key=0) Trunking Forward Port Mask 1 (hash key=1) Trunking Forward Port Mask 2 (hash key=2) Trunking Forward Port Mask 3 (hash key=3) Trunking Forward Port Mask 4 (hash key=4) Trunking Forward Port Mask 5 (hash key=5) Trunking Forward Port Mask 6 (hash key=6) Trunking Forward Port Mask 7 (hash key=7) IP multicast MAC address signature Low Register - Byte [3:0] IP multicast MAC address signature High Register - Byte [5:4] IP multicast MAC address Mask Low Register - Byte[3:0] IP multicast MAC address Mask High Register - Byte[5:4] FCB Handle Register for CPU CPU Internal RAM Command Register CPU Internal RAM Data Register - 0 Table 8 - MDS212 Register Map (continued) Description Address 670 674 678 67C 600 604 608 60C 610 614 618 61C 620 624 628 5C0 5C4 5C8 5CC 5D0 5D4 5D8 5DC 5E0 5E4 5E8 5EC 5F0 5F4 580 584 588
Data Sheet
W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R --/R W/R W/R
9. Access Control Function Group 2 (Chip Level controls)
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Tag CPUIRDAT1 CPUIRDAT2 CPUIRRDY LEDR ECR0 ECR1 ECR2 ECR3 ECR4 PVIDR Description CPU Internal RAM Data Register - 1 CPU Internal RAM Data Register - 2 Internal RAM Read Ready for CPU LED Register MAC Port Control Register MAC Port Configuration Register MAC Port Interrupt Mask Register MAC Port Interrupt Status Register Status Counter Wrap Signal PVID Register Table 8 - MDS212 Register Map (continued) Address 58C 590 594 598 [N*4]0 [N*4]4 [N*4]8 [N*4]C [N*4+1]0 [N*4+2]4
Data Sheet
W/R W/R W/R --/R W/R W/R W/R W/R --/R --/R W/R
10. Ethernet MAC Port Control Registers - (substitute [N] with Port Number, N = {0..12})
18.2 18.2.1
Register definitions Device Configuration Register GCR - Global Control Register
Zero-Wait-State, h7C0
31 24 23 20 19 16 15 12 11 8 7 SYN 4 3 2 0 Op-Code
18.2.1.1
Access: Address:
Direct Access,
Write only
Bit [2:0]
Op-Code
3-bit Operation Control Code
Op-Code 000 001 010 011 1XX Bit [7:4]
Command Clr RST RESET EXEC ---
Description Clear Device Reset: - Allows state machines to exit from RESET state and to initialize their internal control parameters if necessary. Device Reset: -- Resets all internal state machines of each device and stays in RESET state (except the Processor Bus Interface logic). Execution: -- Allows state machines to start their normal operations. No-Op No-Op Table 9 - Global Control Register
SYN bits, reserved for HISC Usage.
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18.2.1.2
Access: Address:
Data Sheet
DCR0 - Device Status Register
Zero-Wait-State, h7C0
31 1 Status 0
Direct Access,
Read only
Bit [1:0]
Status
2-bit Operation Control Code
* Power-up default = 00 Status 00 01 10 Bit [31:2] Reserved State INIT RESET EXEC Description Initialization: Device is in idle state pending for system software initialization. Device Reset: Device is in RESET state. Execution: Device is under normal operation. Table 10 - Device Status Register
18.2.1.3
Access: Address:
DCR1 - Signature, Revision & ID Register
Non-Zero-Wait-State, Direct Access, h7C4
31 25 24 Dev_ID 20 19 16 15 12 11 Signature 87 4 3 2 Rev 0
Write/Read
Bit [3:0] Bit [7:4] Bit [15:8] Bit [19:16] Bit [24:20] Bit [31:25]
Device Revision Code Reserved Signature Reserved DEV_ID Reserved 5-bit Device ID (Read/Write) 8-bit Device Signature
18.2.1.4
Access: Address:
DCR2 - Device Configuration Register
Non-Zero-Wait-State, h7C8
31 27 26 25 22 21 20 19 18 17 FE and MAC SE Configuration 9 8 7 6 543 2 1 0 MT ML IP SC IP Boot Strap MC
Direct Access,
Write/Read
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Bit [1:0] SC System Clock Rate 00= 100Mhz 10=90Mhz IRQ output polarity control 0 = active low output System Configuration mode 0=Nonblocking (For MDS213, always equal to 0) 1=Blocking Default = 00 01 = 120Mhz 11= 80Mhz Power-up default =0 1 = active high output
Data Sheet
Bit [2] Bit [3]
IP SM
SRAM Memory Characteristics Bit [4] ML Buffer Memory Level, which can be either 2 chips or 4 chips. 0 = 2 memory chips 1 = 4 memory chips Bit [6:5] MT Memory Chip Type 00 = 64K x 32-bit 10 = 256K x 32-bit Reserved Default = 0 Default = 01 01 = 128K x 32-bit 11 = 512K x 32-bit
Bit [8:7]
Search Engine Configuration Bit [9] SE_AGEN Aging enable, if which is true, the old MCT can be aged out. 0 = disable aging Bit [11:10] HM Hashing Mode, each of which uses different bits of MAC address to come up with each bit of hashing key. Default = 00 00=mode 0 0=mode 2 Bit [13:12] HS Hashing Size 00= 8 10= 10 VLAN Aware Switch 0 = VLAN Unaware No IP Multicast 1 = IP Multicast Disable Global Learning Disable, where CPU shall disable global learning before look into it as a whole piece. 1 = Learning Disable Partial Synchronization enable for MAC Table 0= Fully Synchronization for MCT table 01=mode 1 11=mode 3 Default = 01 01= 9 11= TDB Default = 0 1 = VLAN Aware Default = 1 0 =IP Multicast Enable Default = 0 0 = Learning Enable Default=0 1= Partial Synchronization for MCT table Default = 1 1 = enable aging
Bit [14] Bit [15] Bit [16]
VSW NoIPM GLN
Bit [17]
Partial Syn enable
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Bit [18] Reserved
Data Sheet
Frame Engine and MAC Configuration Bit [19] FE_AGEN Aging enable. If true, the memory resources, occupied by the old message, will free up. 0 = disable aging Bit [20] FOF Forward Oversize Frames 0 = Discard oversize frames Default = 1
1 = enable aging Power-up default =0 1 = Forward oversize frames
Bit [21] Bit [22]
Dec_Buffer_CNT BC_EN
Decrements buffer counter. When the software writes "1" to this bit, the Frame Engine decreases buffer counter by one. Buffer counter enable 0 = Disable (no head of line control Status counter enable 0 = collect status in counter disable 0 = Use external PCS 1 = enable
Bit [23]
STA_EN
1 = collect status in counter enable Default=0 1 = Use internal PCS in the chip Default =0 1 = Not Gate off TX_En when Link down Default=0 1= enable
Bit [24]
SEL_PCS
Bit [25]
Link_GT
TX LED will be off when the link is down and this bit is 0 0 = Gate 0ff TX_En when Link down IP Multicast privileges enable: IP multicast traffic has a privilege over regular multicast traffic. 0= disable
Bit [26]
IPMC
Boot Strap Determine by the bootstrap value. Bit [27] Bit [28] BMOD RW Control Bus Mode (Read only bit) Must BE 0 CPU Read/Write Control Polarity Selection Read only bit 0 = R/W# Bit [29] Bit [30] Bit [31] SWM PSD MRDY Switching Mode (Read only bit) 0 = Managed mode Master Device Enable (Read only bit) 1 =Primary Option of merge the RDY and B_RDY as one pin (Read only bit) 0 =merged pin 1 = W/R# Default=1 1 = Unmanaged mode Default=1 0 = Secondary Default=1 1 = separated pins
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18.2.1.5
Access: Address:
Data Sheet
DCR3 - Interfaces Status Register
Zero-Wait-State, h7CC
31 25 24 21 20 16 15 12 11 Que_Stat 87 Mem_Stat 43210
Direct Access,
Read only
Bit [3:0] Bit [7:4] Bit [4] Bit [5] Bit [6] Bit [7] Bit [11:8] Bit [8] Bit [9]
Reserved Mem_Stat BB RE WE Res. Que_Stat IQ_Rdy IQ_Full Buffer Memory Interface Status Buffer Memory Busy, CPU interface is busy accessing Memory Read FIFO Empty, the FIFO that CPU interface reads is empty Write FIFO Empty, the FIFO that CPU writes is empty Reserved Queue Manager Interface Status CPU Input Queue is ready for CPU to write into queue CPU Input Queue is full
Bit [11:10] Reserved Bit [31:12] Reserved
18.2.1.6
Access: Address:
MEMP - Memory Packed Register
Non-Zero-Wait-State, h7DC
31 - 30 17 16 15 NP WCL 87 5 RCL 0
Direct Access,
Write/Read
Bit [7:0] Bit [15:8] Bit [16]
RCL WCL
Read Cycle Limit (Unit is system Clock). Threshold of reads cycle time. Write Cycle Limit (Unit is system Clock). Threshold of writes cycle time. Not Packed NP=0 Enable the feature of memory read/write packed.
Default=16 Default=16 Default=0 NP=1 Disable, memory access will be a pure round-robin scheme.
NP Bit [31:17]
Reserved
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18.2.2 Interrupt Control Registers
Data Sheet
Four 32-bit Control Registers. ISR Access: Address: ISRM Interrupt Status RegisterIdentify the unmasked interrupt request sources Zero-Wait-State, h7E0 Direct Access, Read only
Masked Interrupt Status Reg.Identify the sources of interrupt with masking
Zero-Wait-State, h7E4 Direct Access, Read only
* Access: * Address:
IMSK
Interrupt Mask RegisterDefines the interrupt sources to be masked
Non-Zero-Wait-State, h7E8 Direct Access, Write/Read
* Access: * Address:
* Set bits to 1 to mask the corresponding interrupt sources
IAR
Interrupt Acknowledgment Reg.Clear the interrupt request bits
* s Access: * s Address: Non-Zero-Wait-State, h7EC Direct Access, Write only * s Set bits to 1 to clear the corresponding interrupt sources
All 4 registers have a common register format and bit assignment
31 25 24 23 MC T MAC_Port Interrupt Interrupt MAC port mapping bit/port 11 10 FM L 9 8 7 654 3 2 1 0
HI MA SC IL
BPFC DB BS CP IL R R Q
Interrupt Source
Interrupt Sources (The following bits need to be redefined.) Bit [0] Bit [1] Bit [2] Bit [3] Bit [4] Bit [5] Bit [6] Bit [7] Bit [8] Bit [9] Bit [10] CPU_Q_Out BSR Double R FCB_Low HISC_BP Reserved Reserved MAIL_ARR HISC_TO Reserved FML_Av Link manager informs CPU that at least 16 Free Mail entry available after CPU encounters empty Free Mail list situation. Bit [23:11] MAC_PORT Interrupt from MAC ports Bit [11] for Port 0, Bit [12] for Port 1 ... Bit [23] for port 12, port 12 is a Giga port Mail arrived from HISC HISC Timeout Interrupt CPU output queue level interrupt Bad switch response Double Release FCB Low HISC instruction pointer matched with Breakpoint Register
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Bit [24] MCT Search Engine found looped MCT Chain. Bit [31:25] Reserved
Data Sheet
Note: MAIL_ARR, CPU_Q_Out and interrupts cannot be cleared by the CPU. They will be cleared whenever their queues are emptied.
18.2.3 18.2.3.1
Access: Address:
Buffer Memory interface register MWARS - Memory Write Address Register - Single Cycle
Zero-Wait-State, h780
31 28 27 26 24 23 22 21 20 I/E Address MA[20:3] 321 0 SP LK BE[3:0] 00001
via FIFO,
Write
Bit [0] Bit [1] Bit [20:2] Bit [21] Bit [22]
LK SP MA [20:2] Reserved I/E
Lock Flag (for internal memory only)LK=0 UnlockLK=1 Lock Swap Byte Order Buffer memory address Bit [20:2] - (Bit [1:0] = 00)
Indicates the Address is Internal or External memory I/E=0 Internal memory I/E=1 External memory
Bit [27:23] Count Bit [31:28] BE [3:0] CPU Bus Type Little Endian Big Endian
Must be 00001 Byte lane enables Bit [31] BE [3] BE [0] Bit [30] BE [2] BE [1] Bit [29] BE [1] BE [2] Bit [28] BE [0] BE [3]
18.2.3.2
Access: Address:
MRARS - Memory Read Address Register - Single Cycle
Zero-Wait-State, h784
31 28 27 24 23 22 21 20 00001 I/E Address MA[20:2] 321 0 SP LK BE[3:0]
via FIFO,
Write
Bit [0] Bit [1] Bit [20:2] Bit [21] Bit [22]
LK SP MA [20:2] Reserved I/E
Lock Flag memory LK=0 Unlock Swap Byte Order Buffer memory address Bit [20:2] (Bit [1:0] = 00) LK=1 Lock
Indicate the Address is Internal or External memory I/E=0 Internal memory I/E=1 External memory
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Bit [27:23] Count Bit [31:28] BE [3:0] Must be 00001 Byte lane enables
Data Sheet
18.2.3.3
Address Registers For Burst Cycle
Two 32-bit burst size registers share a common format * * MWARB
* Address:
Memory Address Register - Burst Write (in D-words) - Maximum 8 D-words
h788
MRARB
* Address:
Memory Address Register - Burst Read (in D-words) - Maximum 8 D-words
h78C
Access:
Zero-Wait-State,
31 28 27 Count I/E
via FIFO,
24 23 22 21 20
Write
321 0 Address MA[20:2] SP LK
Bit [0]
LK
Lock Flag LK=0 Unlock LK=1 Lock
Bit [1] Bit [2] Bit [20:2] Bit [21] Bit [22]
SP Reserved MA [20:2] Reserved I/E
Swap Byte Order
Buffer memory address Bit [20:2] -
(Bit [1:0] = 00)
Indicate the Address is Internal or External memory I/E=0 Internal memory I/E=1 External memory
Bit [27:23] Count
Count = Burst Size in double words Burst size for internal memory is up to 8 D-words. Burst size for external memory is up to 16-Dwords 00001 = 1 D-word, 01111 = 15 D-word ......01000 = 8 D-word 10000= 16 D-word
Valid value range for internal memory is {1 to 8} Valid value range for external memory is {1 to 16} Caution: When setting Count = 16, the Starting address has to be in the Q-word boundary. That is MA[2]=0. Bit [31:28] Reserved
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18.2.3.4 Memory Read/Write Data Registers
Data Sheet
Four 32-bit data registers share a common format * MWDR Memory Write Data Register
via FIFO, Write only * Access: Zero-Wait-State, * Address: h790
*
MRDR
Memory Read Data Register
Direct Access, Read only
* Access: Zero-Wait-State, * Address: h794
Byte Order depends on CPU types * Little Endian CPUs
31 Byte [3] 24 23 Byte [2] 16 15 Byte [1] 87 Byte [0] 0
*
Big Endian CPUs
31 Byte [0] 24 23 Byte [1] 16 15 Byte [2] 87 Byte [3] 0
18.2.3.5
VTBP - VLAN ID Table Base Pointer
Direct Access, Write/Read
Access: Non-Zero-Wait-State, Address:h798
31
17 16 15 VMACB
11 10
9
8
7
6
5
0
VLMS
VLAN ID BASE
Bit [5:0]
VIDB
VLAN ID Table Base, serves as [20:15] bits of address. (VLAN ID Table is 32KB)
Bit [6] Bit [8:7]
Reserved VLMS The size of VLAN MAC Table Default=11 00= reserved 01=16K (for 64 VLANs)
10=32K (for 128 VLANs)11=64K (for 256 VLANs) Bit [15:9] VMACB VLAN MAC Table Base, serves as [20:14] bit of address. This table indicates the association of MAC address and VLAN Bit [31:16] Reserved
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18.2.3.6
Access: Address:
Data Sheet
MBCR - Multicast Buffer Control Register
Non-Zero-Wait-State, h79C
31 22 21 20 19 MCTH MAX_CNT_LMT 11 10 RMC_BUF_RSV 54 MAX_MC_FD 0
Direct Access,
Write/Read
Bit [4:0] Bit [10:5]
MAX_MC_FD RMC_BUF_RSV
Maximum Number of Multicast Frames allowed for forwarding Number of buffers reserved for receiving remote Multicast Frames Maximum Number of Multicast Frames allowed per device Multicast Forwarding Threshold: Watermark for forwarding FF to drop regular multicast packet if IPMC bit in DCR2[26] is ON. CPU can set four level watermarks, which are programmable 00= 25% 10= 75% 01=50% 11= 100%
Bit [19:11] MAX_CNT_LMT Bit [21:20] MCFTH
Bit [31:22] Reserved
18.2.3.7
Access: Address:
AMA - RAM Counter Block Access Register
Non-Zero-Wait-State, h7A0 Direct Access, Write/Read
RAM counter block contains 13 counter blocks (one for each port) Port 0 counter block starts at address 0.) The size of each block is 16 double words, which consist of total 30 statistic counters. has total The size and type of each counter is referred to the register ECR4. CPU uses this register to access the specified statistic counter by setting the start address of RAM counter block and the length.
31 16 15 14 W/ R 11 10 ST_ADR 43 BST_CNT 0
Bit [3:0] Bit [10:4] Bit [14:11] Bit [15]
BST_CNT ST_ADR Reserved W/R
Read/write burst (length) of RAM Block. (Unit = 1double words) Read/Write Start Address.
RAM Block Access Write/Read indicator 1 = Write 0 = Read
Bit [31:16] Reserved Note: The access range is equal to from ST_ADR to END_ADR= S_ADR+ BST_CNT. The END_ADR cannot cross the boundary of each port block, i.e., 8 double words.
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18.2.3.8
Access Address:
Data Sheet
Reserve Register 1
Non-Zero-Wait-State h7B8
31 0x0001 16 15 0x0008 43210
Direct-Access
Write/Read
Must be set to "0X00010008"
18.2.3.9
Access Address:
Reserve Register 2
Non-Zero-Wait-State h7BC
31 25 0x0001 16 15 0x0000 3210
Direct-Access
Write/Read
Must be set to "0X00010000"
18.2.4 18.2.4.1
Access: Address:
Frame Control Buffers Management Register FCBSL - FCB Queue
Non-Zero-Wait-State, h740
31 18 17 Aging Timer Base 11 10 Max # of FCB Buffer 0
Direct Access,
Write/Read
Bit [10:0]
Defines Max # of FCB Buffers Size Range: 1 entry, to 1024 entries
Bit [17:11]
Aging Timer Base
Defines the time interval between scanning of FCB Buffers for aged buffers Aging Time = (Number of valid FCB Buffers* Aging Timer Base) msec
18.2.4.2
Access: Address:
FCBST - FCB QUEUE - Buffer Low Threshold
Non-Zero-Wait-State, h744
31 65 BLowTH 0
Direct Access,
Write/Read
Bit [5:0]
Buf_Low_Th
Buffer Low Threshold - The number of frame control buffer handles left in the Queue to be considered as running low and trigger the interrupt to the CPU.
Bit [31:6]
Reserved
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18.2.4.3
Access Address:
Data Sheet
BCT - (FCB) Buffer Counter Threshold
Non-Zero-Wait-State h74C
31 19 Hi Limit 10 9 Low Limit 0
Direct-Access
Write/Read
Bit[9:0]
Low_Limit
Low limit number of frames to each destination port (i.e., Source port limits the # of FCB used by each destination port)
Bit[19:10]
HI_Limit
High limit number of frames to each destination port (i.e., Source port limits the # of FCB used by each destination port)
18.2.4.4
Access Address:
BCHL - Buffer Counter Hi-low Selection
Non-Zero-Wait-State h750
31 25 Rp_Hi_Low Sel 13 12 Lp_Hi_Low Sel 0
Direct-Access
Write/Read
Bit[12:0]
Lp_Hi_Low Sel
Selection for Low or High Limit of Buffer Counter for Local device 13 bits maps to 13 ports in Local Device 1 = select hi limit 0 = select low limit
Bit[25:13]
Rp_Hi_Low Sel
Selection for Low or High Limit of Buffer Counter for Remote device 13 bits maps to 13 ports in Remote Device 1 = select hi limit 0 = select low limit
18.2.5 18.2.5.1
Access: Address:
Queue Management Register CINQ - CPU Input Queue
Non-Zero-Wait-State, h708
31 32-bit data from CPU input queue 0
Direct Access,
Write only
Note: Check IQ_RDY=1 in DCR3 (Interface Status Register) before writing into CPU Input Queue
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18.2.5.2
Access: Address:
Data Sheet
COTQ - CPU Output Queue
Non-Zero-Wait-State, h70C
31 30 CPU Output Queue Entry 0
Direct Access,
Read only
Bit [30:0] Bit [31]
31-bit CPU Output Queue Entry Status queue is ready
18.2.6 18.2.6.1
Access: Address:
Switching Control register HPCR - HISC Processor Control Register
Non-Zero-Wait-State, h6C0
31 321 0
Direct Access,
Write/Read
RS LD HT
Bit [0]
HT
Halt the HISC processor from execution Not Apply for non-managed mode (It can be fixed in next cut.)Power-up default = 1
Bit [1]
LD
Switch the Micro-Code Memory from instruction fetch mode to downloading mode
Bit [2]
RS
Reset IP to 0 - (Write only bit) (This bit is auto reset to 0 after IP is reset to 0)
Bit [31:3] RS 1 0 0 1 0 1 LD 0 0 1 0 0 1
Reserved HT 1 1 X 0 0 X State INIT HALT LOAD START EXEC -Description Initialization State: -- Stopped HISC execution, reset IP to 0. Halt State: -- Stopped HISC execution, waiting for HT=0. Micro-Code Loading State: -- Stopped HISC execution, increment IP for every Wr/Rd to HMPC Start State: -- Reset IP=0, and start HISC execution. Execution State: -- Continue HISC execution without reset IP. Illegal State.
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18.2.6.2
Access: Address:
Data Sheet
HMCL0 - HISC Micro-code Loading Port - Low
Non-Zero-Wait-State, h6C4
31 19 HISC Instruction Word [31:0] 0
Direct Access,
Write/Read
Loading micro code into HISC.
Bit [31:0]
HISC Instruction Word [31:0]
HISC Instruction Word has total 40 bit-wide. Needs to be broken into two registers.
18.2.6.3
Access: Address:
HMCL1 - HISC Micro-code Loading Port - High
Non-Zero-Wait-State, h6C8
31 87 HISC Instruction [39:32] 0
Direct Access,
Write/Read
Bit [7:0] Bit [31:8]
HISC Instruction Word [39:32] Reserved
18.2.6.4
Access: Address:
MS0R Micro Sequence 0 Register
Zero-Wait-State, h6D4
31 24 23 16 15 DataBit[31:0] 87 0
Direct Access,
Write/Read
Bit [31:0]
Data Bit [31:0] to the sequencer RAM (The length of Micro Sequence Data is 54-bit, Need to be broken into tow registers)
18.2.6.5
Access: Address:
MS0R Micro Sequence 1 Register
Zero-Wait-State, h6D8
31 Cnt 29 28 20 19 Data bit[51:32] 0
Direct Access,
Write/Read
Bit [19:0]
Data Bit [51:32] to the sequencer RAM (Write only bits)
Bit [31:29] CNT Control bits 000 NOP
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001 010 011 100 101 110 Load Restart Ptr IncAdr Halt UnLoad UnHalt
Data Sheet
Bit [28:20] Reserved
18.2.6.6
Access: Address:
Flooding Control Register
Non-Zero-Wait-State, h6DC
31 24 23 16 15 14 Unicast to CPU rate 12 11 Time Base U2MR 87 Multicast to CPU rate 0
Direct Access,
Write/Read
Bit [7:0]
M2CR
Multicast to CPU Rate Restricts the number of frames within the Time window defined in bit[15:12]
Bit [11:8]
U2MR
Unicast to Multicast Rate Restricts the number of flooding unicast frames within the Time window
Bit [14:12] Time Base Defines the time window used by M2CR and U2MR 000 = 100us 100 = 1.6ms Bit [15] Reserved Unicast to CPU Rate Restricts the number of frames within the Time window defined in bit[15:12] Bit [31:24] Reserved 001 = 200us 010 = 400us 101 = 3.2ms 110 = 6.4ms 011 = 800us 111 = 100us
Bit [23:16] U2CR
18.2.6.7
Access: Address:
MCAT - MCT Aging Timer
Non-Zero-Wait-State, h6E0
31 20 19 MCT Aging Timer 0
Direct Access,
Write/Read
Bit [19:0]
When the value is reached, it ages out Default=0 msec (unit=msec) Must be configured to not zero value. Suggestion value: 5msec.
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18.2.6.8
Access: Address:
Data Sheet
Tpmxr - Trunk Port Mapping Table Index Register
Non-Zero-Wait-State, h6E4
31 87 Entry Index 0
Direct Access,
Write/Read
For Trunk port mapping Table pointer
Bit [7:0] Bit [31:8] Reserved
8-bit Table entry Index Value set to 0
18.2.6.9
Access: Address:
TPMTD - Trunking Port Mapping Table Data Register
Non-Zero-Wait-State, h6E8
31 5 43 DV Port ID 0
Direct Access,
Write/Read
Bit [3:0] Bit [4] Bit [31:5]
Port ID DV Reserved
Trunking port Device ID
18.2.6.10
Access Address:
PTR - Pacing Time Regulation
Non-Zero-Wait-State h6EC Direct-Access Write/Read
Use for Pacing traffic to Remote Ports via XpressFlow Pipe or Local transmission
31 16 15 12 11 UC_TM 8 7 G_TM 43 100_TM 0
MC_TM
Bit [3:0] Bit [7:4] Bit [11:8] bit[ 15:12]
100_TM g_TM mc_TM uc_TM
100M port timer Gigabit port timer Multicast timer Unicast timer
Default =5 Default =6 Default =5 Default =5
Unit time = 80 nsec.(for 64 Bytes Frame.) Note that Frame Engine determine the tic value dependent upon the frame. If short frame, it takes above value. For long frame (> 64 frame), it will double the above value as the reference. Bit [31:16] Reserved
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18.2.6.11
Access: Address:
Data Sheet
MTCR - MCT Threshold & Counter Register
Non-Zero-Wait-State, h6F0
31 22 21 MCT threshold 11 10 0
Direct Access,
Write/Read
Bit [10:0] Bit [21:11] Bit [31:22]
Reserved MCT Threshold Reserved Alert system when free MCT entries are below this threshold
18.2.7 18.2.7.1
Access: Address:
Link List Management LKS - Link List Status Register
Zero-Wait-State, h680
31 43 2 1 0
Direct Access,
Read only
Bit [0]
Mail Box is not ready for CPU to send entry to HISC 1=Not Ready0=Ready
Bit [1]
Free Mail Box is not ready for CPU to put entry into 1= Not Ready0=Ready
Bit [2]
CPU gets Mail from HISC 1= Ready0=Not Ready
Bit [3]
Free Mail Box has entry for CPU to get 1=Ready 0=Not Ready
Bit [31:4]
Reserved
18.2.7.2
Access: Address:
AMBX - Mail Box Access Port
Zero-Wait-State, h684 Direct Access, Write/Read
In write mode, CPU sends Mail to HISC In Read mode, CPU receives Mail from HISC
31 30 21 20 Entry Handle 21 0 0
00
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Zarlink Semiconductor Inc.
MDS213
Bit [20:0] Bit [29:21] Reserved Bit [30] Bit [31] Link List is Empty. (Read only) Link List is Ready. (Same as bit [0] of LKS register) (Read only) Entry handle, the bit [2:0] always 2'b000
Data Sheet
18.2.7.3
Access: Address:
AFML - Free Mail Box List Access Port
Zero-Wait-State, h688
31 30 21 20 Entry Handle 21 0 0
Direct Access,
Write/Read
00
Bit [20:0]
Entry handle, the bit [2:0] always 2'b000
Bit [29:21] Reserved Bit [30] Bit [31] Link List is Empty. (Read only) Link List is Ready. (Same as bit [1] of LKS register) (Read only)
18.2.8 18.2.8.1
Access: Address:
Access Control Function AVTC - VLAN Type Code Register
Non-Zero-Wait-State, h648
31 P7 P6 P5 P4 P3 P2 P1 16 15 P0 VLAN Type Code 0
Direct Access,
Write/Read
Bit [15:0] Bit [31:16]
2-byte VLAN Type Code defined by IEEE 802.1Q VLAN Standard Priority 4 level priority denoting by 2-bit for each Mapping 8 level VLAN priorities to 4 level internal priorities.
18.2.8.2
Access: Address:
AXSC - Transmission Scheduling Control Register
Non-Zero-Wait-State, h64C
31 12 11 QSW2 87 QSW1 43 QSW0 0
Direct Access,
Write/Read
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Bit [11:0] QSW[2:0]
Data Sheet
Transmission Queue Service Weight for queue 2, 1 & 0. (4 bit each) Defines the service rate for each queue QR0-QR3 QR0 : QR1 : QR2 : QR3 QR0 = QSW0*(QSW1+1)* (QSW2+1) QR1 = QSW1*(QSW2+1) QR2 = QSW2 QR3 = 1
Note: Queue 0 has the highest priority. Queue Size is defined in the Queue Control Table
18.2.8.3
Access: Address:
ATTL - Transmission Timing Control
Non-Zero-Wait-State, h650
31 22 21 14 13 TxFIFO Threshold[7:0] depart_time 54 qmt_cnt 0
Direct Access,
Write/Read
Bit [4:0] Bit[13:5] Bit [21:14] TXFIFOT
Transmission queue aging time out counter frame latest departure time Transmission FIFO Threshold in Bytes (Default =0) Only for 100M ports Unit=8Bytes 0= Cut Through at the destination 100M port When the value does not equal zero, it indicates the port cannot start sending frames out, until the Tx FIFO reaches the threshold or EOF.
18.2.9
MII Serial Management Channel
These registers are part of the Management Module. They allow the upper layer services to communicate with any one of the PHYs that are connected to the Management Module through the serial interface.
18.2.9.1
AMIIC - MII Command Register
This is a write-only register. The upper layer services write the management frame to be sent to the PHYs into this register. The MSB (bit 31) is the first bit sent over the serial interface. Access: Address: Non-Zero-Wait-State, h654
31 30 29 28 27 ST OP PHY_AD 23 22 REG_AD 18 17 16 15 TA DATA (16-bit) 210
Direct Access,
Write only
Bit [31:30] Bit [29:28] Bit [27:23]
ST OP PHY_AD
Start of frame - always = "01" Operation code - "10" for read command and "01" for write command 5-bit PHY Address
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Bit [22:18] Bit [17:16] Bit [15:0] REG_AD TA DATA 5-bit Register Address in PHY Turnaround - "10" for write 16-bit Write Data to PHY
Data Sheet
18.2.9.2
AMIIS - MII Status Register
The upper layer services should read this register for data sent by the PHYs. The lower 16 bits contain data received by the Management Module Access: Address: Non-Zero-Wait-State, h658
31 RY 30 VD 29 16 15 DATA (16-bit) 210
Direct Access,
Read only
Bit [31] Bit [30] Bit [15:0] Bit [31] RDY 1 1 0
RDY VALID DATA Bit [30] VALID 1 0 X
Data Ready Data Valid 16-bit Read Data from PHY
Description Data field contains valid data from the PHYs Data field contains invalid data from the PHYs Data field is not ready to be read by Switch Manager CPU
18.2.10 18.2.10.1
Access: Address:
Flow Control Management AFCRIA - Flow Control RAM Input Address
Non-Zero-Wait-State, h65C
31 32 address 0
Direct Access,
Write only
Bit [2:0]
3-bit address for the RAM in MAC storing flow control frame
Usage: Flow Control Frame consists of 64 Bytes. Using AFCRIA and AFCRID0-1, the CPU loads 8 bytes each time. The CPU specifies the address in AFCRIA and writes the content of 4 bytes in AFCRID0 and 4 Bytes in AFCRID1. Then repeats the above procedure 8 times to load a whole flow control frame into the Chip.
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18.2.10.2
Access: Address:
Data Sheet
AFCRID0 - Flow Control RAM Input Data 0
Non-Zero-Wait-State, h660
31 Content of Input Flow Control Frame[31:0] 0
Direct Access,
Write only
Bit [31:0]
Content of flow control frame [31:0], Flow Control Frame has 64 bytes and is defined by IEEE
18.2.10.3
Access: Address:
AFCRID1 - Flow Control RAM Input Data 1
Non-Zero-Wait-State, h664
31 Content of Input Flow Control Frame[63:32] 0
Direct Access,
Write only
Bit [31:0]
Content of flow control frame [63:32]
18.2.10.4
Access: Address:
AFCR - Flow Control Register
Non-Zero-Wait-State, h670
31 16 15 14 13 12 10 9 **** 0 XN F AE XON_Th E d
Direct Access,
Write/Read
Bit [9:0]
Reserved
Bit [12:10] XON_ThdDefines the minimum # of free Frame Buffers before transmitting XON flow control frame.
Bit [13] Bit [14]
Queue Aging Enable Flush Enable
TX queue aging function enable When stack is full, enable flush procession 0 = disable 1 = enable
Bit [15]
XON Enable
Full Duplex XON enable 0 = disable 1 = enable
Bit [31:16] Reserved
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18.2.10.5 AMAR[1:0] - Multicast Address Reg. For MAC Control Frames
Data Sheet
This 6-byte MAC Address is stored in two 32-bit registers * * * * AMAR0 MAC Address Byte [3:0] Address: h674 AMAR1 MAC Address Byte [5:4] Address: h678 Non-Zero-Wait-State,
31 AMAR0 AMAR1 MAC 3 24 23 MAC 2
Access:
Direct Access,
16 15
Write/Read
87 MAC 1 MAC 5 MAC 0 MAC 4 0
18.2.10.6
Access: Address:
AMCT - MAC Control Frame Type Code Register
Non-Zero-Wait-State, h67C
31 24 23 16 15 87 Frame Type 0
Direct Access,
Write/Read
*
2-byte MAC Control Frame Type Code defined by IEEE 802.3X Full Duplex Flow Control Standard
18.2.10.7
ADAR [1:0] - Base MAC Address Registers
The 6-byte MAC Address is stored in two 32-bit registers * * * * ADAR0 MAC Address Byte [3:0] Address: h600 ADAR1 MAC Address Byte [5:4] Address: h604 Non-Zero-Wait-State,
31 AMAR0 AMAR1 MAC 3
Access:
Direct Access,
24 23 MAC 2
Write/Read
16 15 11 MAC 1 MAC 5 0000 87 3 MAC 0 MAC 4 0
* * *
These two registers define the base MAC address of the device. Bit [3:0] of Byte 0 (MAC5) is always set to 0. MAC address for each port is defined by
* MAC Address for Port n = Base MAC Address + MAC Offset [n] where n = {0..12} * MAC Offset[n] is defined by the following registers
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18.2.10.8 ADAOR0 - MAC Offset Address Register 0
Data Sheet
MAC Offset Address for Port [7:0], 4-bit per port Access: Address: Non-Zero-Wait-State, h608
31 28 27 24 23 20 19 16 15 12 11 87 43 0 Port7_offset Port6_offset Port5_offset Port4_offset Port3_offset Port2_offset Port1_offset Port0_offset
Direct Access,
Write/Read
Bit [3:0] Bit [7:4] Bit [11:8] Bit [15:12] Bit [19:16] Bit [23:20] Bit [27:24] Bit [31:28]
MAC Offset address for Port 0 MAC Offset address for Port 1 MAC Offset address for Port 2 MAC Offset address for Port 3 MAC Offset address for Port 4 MAC Offset address for Port 5 MAC Offset address for Port 6 MAC Offset address for Port 7
Usage: There are three ways to assign the MAC address to each port. All ports in the same device share the 44 MSBs, MAC[47:4] in ADAR[0:1], while the 4 LSBs, MAC Offset [3:0] can be assigned as follows: 1. 2. 3. 4. In a managed system, if the device does not support port trunking, MAC_Offset[3:0]= the port number. In a managed system where device supports port trunking, the ports in the same trunk group shares the same MAC[3:0]. The value of MAC[3:0] is assigned by the smallest port number in the Trunk Group. In a managed system, if BIT [18] of DCR2, SMAC=0, all ports are assigned to a single MAC. In an unmanaged system, MAC[3:0] is fixed for all devices (i.e., only one MAC[3:0] address for the whole system).
18.2.10.9
ADAOR1 - MAC Offset Address Register 1
MAC Offset Address for Port [12:8], 4-bit per port Access: Address:
31
Non-Zero-Wait-State, h60C
20 19
Direct Access,
16 15
Write/Read
12 11 87 43 Port8_offset 0
Port12_offset
Port11_offset
Port10_offset Port9_offset
Bit [3:0] Bit [7:4] Bit [11:8] Bit [15:12] Bit [19:16] Bit [31:20]
MAC Offset address for Port 8 MAC Offset address for Port 9 MAC Offset address for Port 10 MAC Offset address for Port 11 MAC Offset address for Port 12 Reserved
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18.2.10.10
Access: Address:
Data Sheet
ACKTM - Timer For SOF Checking
Non-Zero-Wait-State, h610 Direct Access, Write/Read
0 XOFF_CKTM
31
10 9
Bit [9:0]
XOFF_CKTM
The time out value to check SOF after XOFF
Bit [31:10] Reserved Note that the purpose of this timer is to avoid continuously sending the XOFF frames. The XOFF Frame is triggered by the incoming frames when no resources are available in the DS chip. Ideally, after the first XOFF frame is sent out, we expect no frames to be received until we send out the XON frame. However, the connected device may not interpret XOFF frames correctly (or may react slowly) and still keep sending data frames to this congested port. In this case, the congested port will want to send another XOFF frame each time another frame is received. To avoid this scenario, we set the ACKTM timer to prevent the congested port from sending XOFF frames for every incoming frame in congestion period before the timer expires.
18.2.10.11
Access: Address:
31
AFCHT10 - Flow Control Hold Time Of 10Mbps Port
Non-Zero-Wait-State, h620
16 15 HBK_TM_10 0
Direct Access,
Write/Read
Bit [15:0]
HBK_TM_10
Holding time to remote station for 10Mbps port when the chip detects the head of line blocking counter has run out. The holding time value is embedded in the flow control frame sent to the remote station.
Bit [31:16] Reserved
18.2.10.12
Access: Address:
31
AFCHT 100 - Flow Control Hold Time Of 100Mbps Port
Non-Zero-Wait-State, h624
16 15 HBK_TM_100 0
Direct Access,
Write/Read
Bit [15:0]
HBK_TM_100
Holding time to remote station for 100Mbps port when the chip detects the head of line blocking counter has run out. The holding time value is embedded in the flow control frame sent to the remote station.
Bit [31:16] Reserved
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18.2.10.13
Access: Address:
31
Data Sheet
AFCHT1000 - Flow Control Hold Time of Giga Port
Non-Zero-Wait-State, h628
16 15 HBK_TM_G 0
Direct Access,
Write/Read
Bit [15:0]
HBK_TM_G
Holding time to remote station for 1000Mbps port when the chip detects the head of line blocking counter has run out. The holding time value is embedded in the flow control frame sent to the remote station.
Bit [31:16] Reserved
18.2.10.14
Access: Address:
AFCOFT10 - Flow Control Off Time of 10Mbps PROT
Non-Zero-Wait-State, h614 Direct Access, Write/Read
31
24 23
16 15 FL_OFF_10M
0
Bit [15:0]
FL_OFF_10M
Off time to the remote station for 10Mbps Port when the chip detects the buffer resource is not available. The OFF time value is embedded in the flow control frame sent to the remote station.
Bit [31:16] Reserved
18.2.10.15
Access: Address:
31
AFCOFT100 - Flow Control Off Time of 100Mbps PORT
Non-Zero-Wait-State, h618
24 23 16 15 FL_OFF_100M 0
Direct Access,
Write/Read
Bit [15:0]
FL_OFF_100M
Off time to remote station for 100Mbps Port when the chip detects the buffer resource is not available. The OFF time value is embedded in the flow control frame sent to the remote station.
Bit [31:16] Reserved
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18.2.10.16
Access: Address:
31
Data Sheet
AFCOFT1000 - Flow Control Off Time of Giga Port
Non-Zero-Wait-State, h61c
24 23 16 15 FL_OFF_G 0
Direct Access,
Write/Read
Bit [15:0]
FL_OFF_G
Off time to remote station for 1000Mbps Port when the chip detects the buffer resource is not available. The OFF time value is embedded in the flow control frame sent to the remote station.
Bit [31:16] Reserved
18.2.11 18.2.11.1
Access: Address:
Access Control Function Group 2 (Chip Level) APMR- PORT MIRRORING REGISTER
Non-Zero-Wait-State, h5C0
31 15 14 MP 0 13 12 Rx/ L/R Tx 11 Mirror Port 0
Direct Access,
Write/Read
Bit [11:0] Bit [12]
Mirr_Port Local/Remote
The 10/100 port chosen to be mirrored Indicates the mirrored port is from a local or remote device. 0=local 1=remote
(Note Not support 1G port Mirroring.) Bit [13] Bit [14] Rx/Tx MP0 Indicates whether the mirror is receiving data or transmitting data Mirror to Port 0 (Default=0)
MP0=1 Mirror to port 0 MP0=0 Mirror not go to port 0 Bit [31:15] Reserved
18.2.11.2
Access: Address:
PFR - Protocol Filtering Register
Non-Zero-Wait-State, h5C4
31 16 15 87654 3 2 1 0
Direct Access,
Write/Read
The Search Engine will provide ingress filtering on a per-devise basis. Each bit of PF register (default value = 0) will cause packets matching that category to be dropped.
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Bit [7:0] Bit [0] Bit [1] Bit [2] Bit [3] Bit [4] Bit [5] Bit [6] Bit [7] Bit [15:8] Bit [8] Bit [9] Bit [10] Bit [11] Bit [12] Bit [13] Bit [14] Bit [15] Protocol Filter for Unicast Frames IP - Ethernet II encapsulation IP - 802_SNAP encapsulation IPX - Ethernet II encapsulation IPX - 802_SNAP encapsulation IPX - 802.2 encapsulation IPX - 802.3_RAW encapsulation Other (Packets with unknown encapsulation, or non-IP, non-IPX packets) Untagged Frames Protocol Filter for Multicast Frames Multicast IP - Ethernet II encapsulation Multicast IP - 802_SNAP encapsulation Multicast IPX - Ethernet II encapsulation Multicast IPX - 802_SNAP encapsulation Multicast IPX - 802.2 encapsulation Multicast IPX - 802.3_RAW encapsulation Multicast Other (Packets with unknown encapsulation, or non-IP, non-IPX packets) Multicast Untagged Frames
Data Sheet
Bit [31:16] Reserved Usage: There is only one PFR register. For each port there is an enable bit(ECR1 bit 6: IFE- Ingress filter Enable) which determines whether the settings in PFR are applied to that port.
18.2.11.3
THKM [0:7] - Trunking Forwarding Port Mask 0-7
Eight Trunking Hash Key Mask Registers shared the same format. * THKM0 Trunking Forwarding Port Mask 0 Forwarding Port mask for hash key 0
Address:h5C8 * THKM1 Trunking Forwarding Port Mask 1 Forwarding Port mask for hash key 1
Address:h5CC * THKM2 Trunking Forwarding Port Mask 2 Forwarding Port mask for hash key 2
Address:h5D0 * THKM3 Trunking Forwarding Port Mask 3 Forwarding Port mask for hash key 3
Address:h5D4 * THKM4 Trunking Forwarding Port Mask 4 Forwarding Port mask for hash key 4
Address:h5D8 * THKM5 Trunking Forwarding Port Mask 5 Forwarding Port mask for hash key 5
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Address:h5DC * THKM6 Trunking Forwarding Port Mask 6 Forwarding Port mask for hash key 6
Data Sheet
Address:h5E0 * THKM7 Trunking Forwarding Port Mask 7 Forwarding Port mask for hash key 7
Address:h5E4 Access: Non-Zero-Wait-State,Direct Access,Write/Read
31 12 11 TK_MSK 0
Bit [11:0]
TK_MSKPort trunk mask for trunking hash key
Bit [31:12] Reserved CPU sets up this table as follows: 1. Set all bits not in Trunk Groups to 1 2. Set all bits in the Trunk Group to 0 3. Pick one forwarding port per trunk group and turn the corresponding bit to 1 (Each Hash Key may have different forwarding ports, the rule to pick forwarding ports is up to the CPU). Usage: These masks are used to prevent flooded or multicast packets from being transmitted out with more than one port on a trunk. The Trunking Hash Key is used to select the proper mask (for load distribution). The mask value will be set up to mask off all but one port within each trunk group.
18.2.11.4
IPMCAS - IP Multicast MAC Address Signature
Usage: For following four registers IPMCAS0, IPMCAS1, IPMCMSK0 and IPMCMSK1, are used to distinguish between IP multicast traffic and regular multicast. The MAC for IP multicast are h"01:00:5e:00:00:00" to h" 01:00:5e:7f:ff:ff" And the MASK for IPMC is: h"ff:ff:ff:80:00:00". The 6-byte of IP multicast MAC Address is stored in two 32-bit registers * IPMCAS0 IP Multicast MAC Address Byte [3:0]
Address:h5E8 * IPMCAS1 IP Multicast MAC Address Byte [5:4]
Address:h5EC Access: Non-Zero-Wait-State,Direct Access,Write/Read
31 IPMCAS0 IPMCAS1 MAC 3 24 23 MAC 2 16 15 11 MAC 1 MAC 5 87 MAC 0 MAC 4 0
* *
These two registers define the MAC address signature of IP multicast. Default = h" 01:00:5e:7f:ff:ff"
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Zarlink Semiconductor Inc.
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18.2.11.5 IPMCMSK- IP Multicast MAC Address Mask
Data Sheet
The 6-byte of IP multicast MAC Mask is stored in two 32-bit registers * IPMCAS0 IP Multicast MAC Mask Byte [3:0]
Address:h5F0 * IPMCAS1 IP Multicast MAC Mask Byte [5:4]
Address:h5F4 Access: Non-Zero-Wait-State,Direct Access,Write/Read
31 IPMCMSK0 IPMCMSK1 MASK 3 24 23 MASK 2 16 15 11 MASK 1 MASK 5 87 MASK 0 MASK 4 0
These two registers define the MAC Mask of IP multicast. Default = h"ff:ff:ff:80:00:00".
18.2.11.6
Access: Address:
CFCBHDL - FCB Handle Register For CPU Read
Non-Zero-Wait-State, h580 Direct Access, Read only
Usage: When CPU requests a free FDB to write a frame, it must request a free FCB via this register. The register contains a free handle of FCB, which also pointer to a free FDB. CPU reads FCB Handle: (When the CPU write FDB, it requires a FDB handle first). CPU checks CFCBHDL[31],H_RDY ready or not. If so, CPU gets the FCB Handle from CFCBHDL[9:0]
31 H_R DY 10 9 FCB_Handle[9:0] 0
Bit [9:0]
FCB_HANDLE
FCB Handle Address
Bit [30:10] Reserved Bit [31] H_RDY FCB Handle Ready 0=Not Ready 1=Ready
18.2.11.7
CPU Access Internal RAMs (Tables)
Usage: (refer to section 9 for detail). The CPU uses the following methods to access the five internal RAMs, including MCID, VLAN port mapping (VMAP), BM control Table (BMCT), FCB and Transmission Queue control (QCNT). Registers: * * * * * CPUIRCMD: Command register CPUIRDAT0: Data Register for specific entry of content Bit[31:0] CPUIRDAT1: Data Register for specific entry of content Bit[63:32] CPUIRDAT2: Data Register for specific entry of content Bit[95 64] CPUIRRDY: Data Read Ready.
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CPU Reads FCB * * * *
Data Sheet
CPU write the read command into CPUIRCMD with FCB Handle, W/R=0. And set C_RDY. Also, set the table type = FCB, (CPUIRCMD[14]=1) Frame Engine puts the specified FCB content into CPUIRDATL and CPUIRDATM Frame Engine Clear C_RDY Frame Engine set CPUIRRDY[0] to notify CPU that the FCB data is ready to be read.
CPU writes FCB * * * * CPU writes the content of FCB into CPUIRDATL and CPUIRDATM CPU writes the handle of FCB into CPUIRCMD [9:0], set CPUIRCMD [10] = 1,(write CMD), set CPUIRCMD[31]=1, CMD_RDY and set the Table Index to FCB, (CPUIRCMD[14]=1). Frame Engine clears CPUIRCMD [31], C_RDY, when Frame Engine reads FCB done Apply the similar method to access the other four tables.
18.2.11.8
Access: Address:
CPUIRCMD - CPU Internal RAM Command Register
Non-Zero-Wait-State, h584 Direct Access, Write/Read
Command for CPU accesses five internal Tables
31 30 C_R DY 16 15 14 13 12 11 10 9 Entry Index [9:0] 0 QC FC BM VM MC W/ NT B CT AP ID R
Bit [9:0]
Entry Index Type = MCID(16) Type = VMAP(256) Type = BMCT(1K) Type = FCB(1K) Type = QCNT (64)
The index of specified entry Entry index[3:0] Entry index[7:0] Entry index[9:0] Entry index[9:0] Entry index[5:0] Write or Read the table entry 0=Read 1=Write
Bit [10]
W/R
Bit[15:11] Bit[11] Bit[12] Bit[13] Bit[14] Bit[15]
Table bit map MCID VMAP BMCT FCB QCNT
Bit maps of five tables. MCID=1 Use MC ID l Table VMAP=1 Use VLAN port mapping Table (VMAP) BMCT=1 Use Buffer Manager Control Table (BM control) FCB=1 Use FCB Table QCNT=1 Use Transmission Queue control Table (QM control)
Bit [30:16] Reserve Bit [31] C_RDY Command Ready 0=Not Ready 1=Ready
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18.2.11.9 CPUIRDAT - CPU INTERNAL RAM DATA REGISTER
Data Sheet
The 3 data registers are used when CPU reads or writes the content of the specified entry. table * CPUIRDAT0 h588 CPU Internal RAM Data register for Data[63:32] CPU Internal RAM Data register for Data[31:0]
Address: *
CPUIRDAT1 h58C
Address: *
CPUIRDAT2 h590
CPU Internal RAM Data register for Data[95:64]
Address: Access:
31 CPIRDAT0 CPIRDAT1 CPIRDAT2
Non-Zero-Wait-State,
Direct Access,
Write/Read
0
Data[31:0] Data[63:32] Data[95:64]
The content is dependent as to the type of table, as describe follows. Type = MC ID (6bits)
31 CPIRDAT0 65 MCID[5:0] 0
Bit [5:0]
MCID
multicast ID FIFO data output (Note that up to 16 for this version.)
Bit [31:6]
Reserved
Type = VMAP Table (27 bits)
31 CPIRDAT0 27 26 25 RE VLAN TAG Enable [12:0] 13 12 VLAN Port Enable [12:0] 0
Bit [12:0]
VLAN Port Enable [12:0]
one bit for each Ethernet MAC Port Identify the ports associated with each VLAN 0 = disable 1 = enable
Bit [25:13] VLAN Tag Enable [12:0]
one bit for each Ethernet MAC Port 0 = disable 1 = enable
Bit [26]
RE
Remote Ports Enable: Indicate some members in the remote device. 0=disable1=enable
Bit [31:27] Reserved
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Type = BMCT (12bits)
31 CPUIRDAT0 12 11 BM[11:0]
Data Sheet
0
Bit [11:0]
BM
Buffer Management control FIFO Output BM stores free FCB handles. (FCB handle=0 cannot be used.)
Bit [31:12] Reserved Type = FCB (56 bits)
31 CPUIRDAT0 CPUIRDAT1 24 23 FCB_DATA[31:0] FCB_DATA[55:32] 0
Bit [55:0]
FCB
Frame Control Block. Refer to Chapter 9 for detailed data structure.
Type = QCNT (79 bits)
31 CPUIRDAT0 CPUIRDAT1 CPUIRDAT2 WrPt[5:0] ECnt[10:0] CV 15 14 13 Base[11:0] RdPt[9:0] Cache Queue Entry[31:17] 432 0 QS[2:0] WrPT[9:6]
Cache Queue Entry[16:0]
Bit [2:0]
Que_S [2:0]
Queue size
000=128 entries 001=128*2 entries 111=128*8=1K entries Each entry contains 4 bytes
Bit [14:3]
Base [11:0]
Base pointer to its Transmission Queue Entry Count: Total entries in its queue. Write Pointer Address_Write_Entry[20:9]=Base[11:0]+WrPt[9:7] Address_Write_Entry[9:3]= WrPt[6:0] Address_Write_Entry[2:0]= 0 (The address [2:0] is always equal to 0.)
Bit [25:15] ECnt [10:0] Bit [35:26] WrPt [9:0]
Bit [45:36] RdPt [9:0]
Read Pointer Address_Read_Entry[20:9]=Base[11:0]+RdPt[9:7] Address_Read_Entry[9:3]= RdPt[6:0] Address_Read_Entry[2:0]= 0 (The address [2:0] is always equal to 0.)
Bit[46] Bit[78:47]
CV QE[31:0]
Cache Valid CV=1, Cache of Queue Entry QE[31:0] is valid. Cache a queue entry
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Zarlink Semiconductor Inc.
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18.2.11.10
Access: Address:
Data Sheet
CPUIRRDY - Internal Ram Read Ready For CPU
Non-Zero-Wait-State, Direct Access, h594 Write/Read
The Frame Engine sets this ready bit to notify the CPU that the requested data is ready to read.
31 10 RD Y
Bit [0] Bit [31:1]
R_RDY Reserved
Data in Data registers is ready for CPU Read
18.2.11.11
Access: Address:
LEDR- LED Register
Non-Zero-Wait-State, h598 Direct Access, Write/Read
31 30 SS
28 27 26 25 24 23 LCK HT UDEF3
16 15 UDEF2
87 UDEF1
0
Bit [7:0] Bit [15:8]
UDEF1 UDEF2
User defined information status 1 for debug purpose User defined information status 2 for debug purpose User defined information status 3 for debug purpose Holding time for LED signal (Default=00) 00=8msec 10=32msec 01=16msec 11=64msec
Bit [23:16] UDEF3 Bit [25:24] HT
Bit [27:26] LCLK
LED Clock frequency (Default=00) 00= 100M/8=12.5Mhz 10= 100M/32=3.125Mhz 01= 100M/16=6.25Mhz 11= 100M/64-1.5625Mhz
Bit [30:28] Reserve Bit [31] SS Start Shift the status bits out from the master device. This bit has no effect on the slave chip. Note: UDEF1-UDEF3 are used for debug purpose. The contents of UDEF1-3 are loaded by CPU and the usage of these are up to software.
18.2.12
Ethernet MAC Port Control Registers
One set for each Ethernet MAC Port [12:0] MII related controls applies to Port [1:0] only Port 12 is always dedicated to GMAC
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Zarlink Semiconductor Inc.
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18.2.12.1
Access: Address:
Data Sheet
ECR0 - ECR0 - MAC Port Control Register
Non-Zero-Wait-State, h0x0*4 h000 h040 h080 h0c0 h100 h140 h180 h1c0 h200 h240 h280 h2c0 h300 Direct Access, x: port n ECR0_p0 ECR0_p1 ECR0_p2 ECR0_p3 ECR0_p4 ECR0_p5 ECR0_p6 ECR0_p7 ECR0_p8 ECR0_p9 ECR0_p10 ECR0_p11 ECR0_p12
3210 RP RE X R RR
Write/Read
31
Bit [0] Bit [1] Bit [2] Bit [3]
RR XR RE RP
Reset Receiver Reset Transmitter RX Enable RST_PCS, Reset PCS logic (Only apply Gigabit Port)
Port is disabled when both RR & XR bits are set.
18.2.12.2
Access: Address:
ECR1 - MAC Port Configuration Register
Non-Zero-Wait-State, h0x1*4x: port number h004 h044 h084 h0c4 h104 h144 ECR1_p0 ECR1_p1 ECR1_p2 ECR1_p3 ECR1_p4 ECR1_p5 Direct Access, Write/Read
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h184 h1c4 h204 h244 h284 h2c4 h304
31 24 23 IFG
Data Sheet
ECR1_p6 ECR1_p7 ECR1_p8 ECR1_p9 ECR1_p10 ECR1_p11 ECR1_p12
17 16 15 8765432 0
IFE BKUC T TG ID E Configuration Bits Trunking
Port Trunking ID Bits Bit [2:0] Bit [3] TGID TE Group ID Trunk Enable 0= Trunk disable Unicast Blocking Control Bits Bit [5:4] Block_UC_Frame Instructs the Rx MAC to discard incoming Unicast Frames. This feature is used by Spanning Tree. 0X 10 11 Bit [6] IFE Forwarding all frames Ingress Filter Enable Default = 0 Blocking, all frames (Default state) Learning but not forwarding 1= Trunk Enable
Used to enable protocol filtering on a port by port basis. There is only one Protocol Filtering Register (PFR), but it can be used on any combination of ports. 0= disable ingress filter 1= enable ingress filter Physical Layer Control Bits Bit [7] Bit [8] Bit [9] Bit [10] 10M Reserved Full_Duplex FDX_Polarity Enables full duplex modeDefault =0 - Half Duplex Selects the output polarity of Full_Duplex control signal 0 = Low true (Default) Bit [11] Int_Lpback 1 = High true 10M or 100M; 1=10Mbps 0=100Mbps
Setting this bit cause internal connect TXCLK, TXD, TXD[0:3] to RXCLK, RXD, RXD[0:3]
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Default =0 - Disable Bit [12] Ext_Lpback Setting this bit indicate an external loop-back
Data Sheet
(connection of TXCLK, TXD[0:3] to RXCLK, RXD[0:3] are required) Default =0 -- Disable Bit [13] FC_Enable Flow Control EnableDefault =0 - Disable
When enabled: * * In Half Duplex mode, the MAC Transmitter applies back pressure for flow control. In Full Duplex mode, the MAC Transmitter sends Flow-Control frames when necessary. The MAC Receiver interprets and processes incoming Flow Control frames. The MAC Receiver marks all Flow Control Frames. Receive DMA discards the received Flow Control Frame and send status reports to the Switch Manager for statistic collection.
When Disabled: * * The MAC Transmitter does not asserts flow control by sending Flow Control frames nor jamming collision. The MAC Receiver still interprets and processes the Flow-Control frames. The MAC Receiver marks all Flow Control frames. Receive DMA discards the received Flow Control frames and send a status report to the Switch Manager for statistic collection. Link_Polarity Selects the input polarity of Link Status signal 0 = Low true (Default) Bit [15] Tx_Enable 1 = High true
Bit [14]
Enables MAC Transmitter for transmission Default =0 - Disable
Bit [16]
Reserved Inter-frame Gap (Default=7'd24) Use to adjust the inter-frame gap. (Unit =transmit Clock.) The default is 7'd24, stands for 24 transmit clock (each clock transmit 4 bits).
Bit [23:17] IFG
Bit [31:24] Reserved
18.2.12.3
Access: Address:
ECR2 - MAC Port Interrupt Mask Register
Non-Zero-Wait-State, h0x2*4 h008 h048 h088 h0c8 h108 Direct Access, x: port number ECR2_p0 ECR2_p1 ECR2_p2 ECR2_p3 ECR2_p4 Write/Read
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h148 h188 h1c8 h208 h248 h288 h2c8 h308
31
Data Sheet
ECR2_p5 ECR2_p6 ECR2_p7 ECR2_p8 ECR2_p9 ECR2_p10 ECR2_p11 ECR2_p12
210 Mask
Bit [0] Bit [1] Bit [31:2]
WAS Link_Change Reserved
If set, the status counter wrap around signal is masked. If set, the Link_Up and Link_Down Interrupts are masked.
Link Change interrupts are automatically disabled whenever both MAC Transmitter & Receiver are in Reset state i.e. both XR & RR bits are set.
18.2.12.4
Access:
ECR3 - MAC Port Interrupt Status Register
Non-Zero-Wait-State, Direct Access, x: port number ECR3_p0 ECR3_p1 ECR3_p2 ECR3_p3 ECR3_p4 ECR3_p5 ECR3_p6 ECR3_p7 ECR3_p8 ECR3_p9 ECR3_p10 ECR3_p11 ECR3_p12 Read only
Address:h0x3*4 h00c h04c h08c h0cc h10c h14c h18c h1cc h20c h24c h28c h2cc h30c
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Data Sheet
31
3
2
1
0
Status
Bit [0] Bit [1]
WAS Link_Change
Wrapped around signal. This bit is set when the MAC determines that the status of physical link has been changed
Bit [2]
LK_UP
0=Link Down,
1=Link UP
This bit is reset whenever the PHY has identified the lost of physical link integrity. Bit [31:3] Reserved
18.2.12.5
Access: Address:
ECR4 - Port Status Counter Wrapped Signal
Non-Zero-Wait-State, h0x4*4 h010 h050 h090 h0d0 h110 h150 h190 h1d0 h210 h250 h290 h2d0 h310 Direct Access, x: port number ECR4_p0 ECR4_p1 ECR4_p2 ECR4_p3 ECR4_p4 ECR4_p5 ECR4_p6 ECR4_p7 ECR4_p8 ECR4_p9 ECR4_p10 ECR4_p11 ECR4_p12
0 Status Wrapped Signal
Read only
31 30
B[0]. B[1]. B[2].
0-d 1-L 1-U
Bytes Sent(D) Unicast Frames Sent Flow Control Sent
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B[3]. B[4]. B[5]. B[6]. B[7]. B[8]. B[9]. B[10]. B[11]. B[12]. B[13]. B[14]. B[15]. B[16]. B[17]. B[18]. B[19]. B[20]. B[21]. B[22]. B[23]. B[24]. B[25]. B[26]. B[27]. B[28]. B[29]. 2-l 2-U1 2-U2 3-d 4-d 5-d 6-L 6-U 7-l 7-u 8-L 8-U 9-L 9-U A-l A-u B-l B-u C-l C-u D-l D-u E-l E-u F-l F-U1 F-U2 Non-unicast frame sent frame send fail Alignment Error Bytes Received (Good or Bad) (D) Frames Received (Good or Bad) (D) Total Bytes Received (Good) (D) Total Frames Received (Good) Flow Control Frames Received Multicast Frames Received Broadcast Frames Received Frames with length of 64 bytes Jabber Frames Frames with length between 65-127 bytes Oversize Frames Frames with length between 128-255 bytes Frames with length between 256-511 bytes Frames with length between 512-1023 bytes Frames with length between 1024-1528 bytes Undersize Frames Fragment CRC Short Event Collision Drop Filtering Counter Delay exceed discard counter Late Collision
Data Sheet
Note: Each port owns a counter block, containing 16 double words. The 29 bits indicate that each corresponding counter is wrapping around the signal. The type and location of each counter is specified by the following format. The format description: X-Y: X means the relative Physical Address in its counter blocks. : Y indicates the type of counter it is (Notation "C"= double word read from RAM block) D: C[31:0] double word counter
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L: C[23:0] 24 bits counter U: C[31:24] 8 bits counter U1: C[23:16] 8 bits counter U2: C[31:24] bits counter (the same as notation "U") l: C[15:0] 16 bits counter u C[31:16] 16 bits counter
Data Sheet
18.2.12.6
Access: Address:
PVID Register
Non-Zero-Wait-State, h0x9*4 Direct Access, x: port number Write/Read
For Default VLAN ID h024 h064 h0a4 h0e4 h124 h164 h1a4 h1e4 h224 h264 h2a4 h2e4 h324
31
PVIDR_p0 PVIDR _p1 PVIDR _p2 PVIDR _p3 PVIDR _p4 PVIDR _p5 PVIDR _p6 PVIDR _p7 PVIDR _p8 PVIDR _p9 PVIDR _p10 PVIDR _p11 PVIDR _p12
16 15 Priority 13 12 11 Port VLAN ID 0
Bit [0:11] Bit [12]
Port VLAN ID (PVID) Reserved
Bit [15:13] Priority Bit [31:16] Reserved
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19.0
19.1
Data Sheet
DC Electrical Characteristics
Absolute Maximum Ratings
Package: 456 HBGA (Heatslug BGA) Storage Temperature: -65C to +150C Operating Temperature: 0C to +70C Maximum Junction Temperature:125C Supply Voltage VCC with Respect to VSS +3.0 V to +3.6 V Supply Voltage VDD with Respect to VSS +2.38 V to +2.75 V Voltage on 5V Tolerant Input Pins -0.5 V to (VCC + 3.3 V)
Caution: Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability.
19.2
DC Electrical Characteristics
VCC = 3.0 V to 3.6 V (3.3v +/- 10%)TAMBIENT = 0 C to +70 C VDD = 2.5V +10% - 5% Recommended Operating Conditions Symbol Parameter Description Min Type Max Unit
fosc ICC IDD VOH VOL VIH-TTL VIL-TTL IIL IOL CIN COUT CI/O ja ja ja jc
Note 1:
Frequency of Operation Supply Current - @ 100 MHz (VCC =3.3 V) Supply Current - @ 100 MHz (VDD =2.5 V) Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5V tolerant) Input Low Voltage (TTL 5V tolerant) Input Leakage Current (all pins except those with internal pull-up/pull-down resistors) Output Leakage Current Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2 m/s air flow Thermal resistance between junction and case
When external heat sink is attached, JA is reduced by about 8-12% in still air.
100 270 780 2.4 0.4 2.0 VCC + 2.0 0.8 10 10 5 5 7 121 11 9.6 3.3 351 1014
MHz mA mA V V V V A A pF pF pF C/W C/W C/W C/W
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20.0
20.1
Data Sheet
AC Specifications
XPIPE Interface
X_DCLKI X1-max X1-min X_DI[31:0] X4-max X4-min X19 X20 X_DENI X21 X22 X_FCI X_DCLKI X17 X18
X_DCLKO
X_FCO
X3-max X3-min X_DENO X2-max X2-min X_DO[31:0] XPIPE INTERFACE - Output valid delay timing
XPIPE INTERFACE - Input setup and hold timing S_CLK X15 X16 X_DCLK
Figure 26 - XPIPE Interface - Output Valid Delay Timing
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Symbol X1 X2 X3 X4 X15 X16 X17 X18 X19 X20 X21 X22 Parameter X_DCLKO output valid delay X_DO[31:0] output valid delay X_DENO output valid delay X_FCO output valid delay X_DCLKI input set-up time X_DCLKI input hold time X_DI[31:0] input set-up time X_DI[31:0] input hold time X_DENI input set-up time X_DENI input hold time X_FCI input set-up time X_FCI input hold time -100MHZ Min (ns) 1 1 1 1 3 0 3 0 3 0 3 0 Max (ns) 5 5 5 5 Note CL = 30pf CL = 30pf CL = 30pf CL = 30pf
Data Sheet
Reference S-CLK Reference S-CLK
Table 11 - AC Characteristics - XPipe Interface
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20.2 CPU BUS Interface
Data Sheet
P_CLK P19-max P19-min P_D[31:0] P_RST# P23-max P23-min P_ADS# P24-max P24-min P_INT CPU BUS INTERFACE - Output valid delay timing P_CSI# P20-max P20-min P_A[10:1] P21-max P21-min P9 P10 P_A[10:1] P11 P12 P_D[31:0] CPU BUS INTERFACE - Input setup and hold timing P15 P16 P25-max P25-min P_GNTC P26-max P26-min P_REQ1 P_REQC P17 P18 P_RWC# P7 P8 P5 P6 P3 P4 P_CLK P1 P2
P_RDY#
P_RWC#
P22-max P22-min P_ADS#
P_GNT1
Figure 27 - AC Characteristics - CPU BUS Interface
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Zarlink Semiconductor Inc.
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Symbol P_CLK P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P_RST# input setup time P_RST# input hold time P_ADS# input setup time P_ADS# input hold time P_RWC# input setup time P_RWC# input hold time P_CSI# input setup time P_CSI# input hold time P_A[10:1] input setup time P_A[10:1] input hold time P_D[31:0] input setup time P_D[31:0] input hold time P_REQC input setup time P_REQC input hold time P_REQI input setup time P_REQI input hold time P_D[31:0] output valid delay P_A[10:1] output valid delay P_RWC# output valid delay P_ADS# output valid delay P_RDY# output valid delay P_INT output valid delay P_GNTC output valid delay P_GNT1 output valid delay 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 2 2 2 2 2 2 2 2 12 9 9 9 9 9 9 9 CL = 65pf CL = 50pf CL = 50pf CL = 50pf CL = 50pf CL = 30pf CL = 20pf CL = 20pf Parameter -66MHZ Min (ns) Max (ns) Note
Data Sheet
Table 12 - AC Characteristics - CPU Bus Interface
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20.3 Local SBRAM Memory Interface
L_CLK L3-max L3-min
Data Sheet
LOCAL SBRAM MEMORY INTERFACE L_CLK L1 L2 L_D[63:0]
L_D[63:0]
L_A[20:3] LOCAL MEMORY INTERFACE Input setup and hold timing L_ADSC#
L4-max L4-min
L6-max L6-min
L7-max L7-min L_BW[7:0]# L8-max L8-min L_WE[1:0]# L9-max L9-min L_OE[1:0]# LOCAL MEMORY INTERFACE Output valid delay timing
Figure 28 - Local Memory Interface - Input Setup and Output Valid Delay Timing -100MHZ Min (ns) Max (ns)
Symbol L_CLK L1 L2 L3 L4 L6 L7 L8 L9
Parameter
Note CL = 50pf
L_D[63:0] input set-up time L_D[63:0] input hold time L_D[63:0] output valid delay L_A[20:3] output valid delay L_ADSC# output valid delay L_BW[7:0]# output valid delay L_WE[1:0]# output valid delay L_OE[1:0]# output valid delay
3 1.5 2 2 2 2 2 0 7 7 7 7 7 1 CL = 30pf CL = 50pf CL = 50pf CL = 30pf CL = 30pf CL = 30pf
Table 13 - AC Characteristics - Local SBRAM Memory Interface
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M_CLK PM1 PM2 PM_DENI PM3 PM4 PM_D[1:0] PM5
Data Sheet
Figure 29 - Port Mirroring Interface - Input Setup and Hold Timing
M_CLKI PM6-max PM6-min PM_DENO PM7-max PM7-min
PM_DO[1:0]
Figure 30 - Port Mirroring Interface - Output Delay Timing
M_CLKI M1 M2 M[11:0]_RXD[1:0] M3 M4 M[11:0]_CRS_DV M5
Figure 31 - Reduce Media Independent Interface - Input Setup and Hold Timing
M_CLKI M6-max M6-min M[11:0]_TXEN M7-max M7-min
M[11:0]_TXD[1:0]
Figure 32 - Reduce Media Independent Interface - Output Delay Timing
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-50 MHZ Min (ns) Max (ns)
Data Sheet
Symbol PM1 PM2 PM3 PM4 PM5 PM6 PM7 M_CLKI
Parameter
Note Reference Input Clock
PM_DENI Input Setup Time PM_DENI Input Hold Time PM_DI[1:0] Input Setup Time PM_DI[1:0] Input Hold Time PM_DENO Output Delay Time PM_DO[1:0] Output Delay Time
1.5 2 1.5 2 2 2 11 11 CL = 30pf CL = 30pf
Table 14 - AC Characteristics - Port Mirroring Interface
Symbol M1 M2 M3 M4 M5 M6 M7 M_CLKI
Parameter
-50 MHZ Min (ns) Max (ns)
Note Reference Input Clock
M[11:0]_RXD[1:0] Input Setup Time M[11:0]_RXD[1:0] Input Hold Time M[11:0]_CRS_DV Input Setup Time M[11:0]_CRS_DV Input Hold Time M[11:0]_TXEN Output Delay Time M[11:0]_TXD[1:0] Output Delay Time
1.5 2 2 1 2 2 11 11 CL = 30pf CL = 30pf
Table 15 - AC Characteristics - Reduced Media Independent Interface
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Data Sheet
M[12]_RXCLK M[12]_RXD[7:0] G1 G3 M[12]_RX_DV G5 M[12]_RX_ER G7 M[12]_CRS G9 M[12]_COL G10 G8 G6 G4 G2
M[12]_TXCLK G11-max G11-min G12-max G12-min G13-max G13-min
M[12]_TXD[7:0]
M[12]_TX_EN
M[12]_TX_ER
Output Valid Delay Timing
Input Setup and Hold Timing
Symbol
Parameter M[12]_RXCLK
-125 MHZ Min (ns) Max (ns)
Note Input Reference Clock
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10
M[12]_RXD[7:0] Input Setup Times M[12]_RXD[7:0] Input Hold Times M[12]_RX_DV Input Setup Times M[12]_RX_DV Input Hold Times M[12]_RX_ER Input Setup Times M[12]_RX_ER Input Hold Times M[12]_CRS Input Setup Times M[12]_CRS Input Hold Times M[12]_COL Input Setup Times M[12]_COL Input Hold Times M[12]_TXCLK
2 0 2 0 2 0 2 0 2 0 Output Reference Clock 1 1 1 5 5 5 CL = 20pf CL = 20pf CL = 20pf
G11 G12 G13
M[12]_TXD[7:0] Output Delay Times M[12]_TX_EN Output Delay Times M[12]_TX_ER Output Delay Times
Table 16 - AC Characteristics - Gigabit Media Independent Interface
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Data Sheet
GP_RXCLK0 /GP_RXCLK1
GP1
GP_RXD[9:0]
GP2
Figure 33 - Input Setup and Hold Timing
GP_TXCLK
GP3-max GP3-min
GP_TXD[9:0]
Figure 34 - Output Valid Delay Timing -125 MHZ Min (ns) Max (ns)
Symbol
Parameter
Note
GP_RXCLK0/ GP_RXCLK1 GP1 GP2 GP_RXD[9:0] Input Setup Times GP_RXD[9:0] Input Hold Times GP_TXCLK 2 0
Input Reference Clock
Output Reference Clock 1 5 CL = 20pf
GP3
GP_TXD[9:0] Output Delay Times
Table 17 - AC Characteristics - Physical Media Attachment Interface
LED_CLKO
LE1 LE2-max LE2-min
LED_DO LE3-max LE3-min
LED_SYNCO
Figure 35 - LED Interface - Output Delay Timing
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Zarlink Semiconductor Inc.
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Variable Freq. Min (ns) Max (ns)
Data Sheet
Symbol
Parameter
Note
LE1 LE2 LE3
LE_CLKO LE-DO Output Valid Delay LE_SYNCO Output Valid Delay -1 -1 7 7
Reference Output Clock CL = 30pf CL = 30pf
Table 18 - AC Characteristics - LED Interface
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E1
E
DIMENSION A A1 A2 D D1 E E1 b e
MIN MAX 2.20 2.46 0.50 0.70 1.17 REF 35.20 34.80 30.00 REF 35.20 34.80 30.00 REF 0.60 0.90 1.27 456 Conforms to JEDEC MS - 034
e D1 D
A2 A1 A
1. CONTROLLING DIMENSIONS ARE IN MM 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. N IS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0.56 MM
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes:
ISSUE ACN DATE APPRD.
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Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
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